Package substrate and flip-chip package circuit including the same

Patent metadata

Field	Value
Publication number	US-11081435-B2
Application number	US-201815860817-A
Country	US
Kind code	B2
Filing date	Jan 3, 2018
Priority date	Jun 17, 2014
Publication date	Aug 3, 2021
Grant date	Aug 3, 2021

Abstract

This disclosure provides a package substrate, a flip-chip package circuit, and their fabrication methods. The package substrate includes: a first wiring layer having a first dielectric material layer and a first metal wire protruding from the first dielectric material layer; a conductive pillar layer formed on the first wiring layer and including a molding compound layer, a second dielectric material layer formed on the molding compound layer, and a metal pillar connected to the first metal wire; a second wiring layer formed on the conductive pillar layer and including a second metal wire connected to the metal pillar; and a protection layer formed on the second wiring layer.

First claim

What is claimed is:

1. A method of fabricating a package substrate, comprising:
(A) providing a carrier;
(B) forming a first wiring layer on the carrier, wherein the first wiring layer includes a first metal wire with a first thickness and a first dielectric material layer with the first thickness, and the first metal wire is constructed with a photolithography process;
(C) forming a conductive pillar layer on the first wiring layer, comprising a metal pillar, a molding compound layer, and a second dielectric material layer, wherein the metal pillar is constructed with the photolithography process and connected to the first metal wire, the molding compound layer and the second dielectric material layer are sequentially formed, the molding compound layer is placed above and covers the first wiring layer and the first dielectric material layer, the molding compound layer is also adjacent to the metal pillar and cover a lower portion of a side surface of the metal pillar, and the second dielectric material is placed above and covers the molding compound layer and the metal pillar, then the second dielectric material layer is partly removed for only covering an upper portion of the side surface of the metal pillar and for exposing a top surface of the metal pillars;
(D) forming a second wiring layer including a second metal wire on the conductive pillar layer, wherein the second metal wire is constructed with the photolithography process and is connected to the metal pillar;
(E) forming a protection layer on the second wiring layer to cover the second metal wire, and removing the carrier; and
(F) removing a part of the first dielectric material layer for the first metal wire to protrude from the first dielectric material layer.

2. The method according to claim 1 , wherein the first dielectric material layer is partly removed in step (F) to form a protrusion part having a decreasing width from top to bottom.

3. The method according to claim 1 , wherein the first dielectric material layer is partly removed in step (F) to form a protrusion part having a concave side wall.

4. The method according to claim 1 , wherein the first dielectric material layer is partly removed in step (F) to form a protrusion part having a side surface completely covered by the first dielectric material layer.

Assignees

• Phoenix Pioneer Technology Co Ltd

Inventors

• Hsu Che-Wei
• Hsu Shih-Ping

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title