Electronic circuit, in particular capable of implementing a neural network, and neural system

Patent metadata

Field	Value
Publication number	US-11080593-B2
Application number	US-201414910984-A
Country	US
Kind code	B2
Filing date	Sep 29, 2014
Priority date	Oct 4, 2013
Publication date	Aug 3, 2021
Grant date	Aug 3, 2021

Abstract

An implementation of neural networks on silicon for the processing of various signals comprises multidimensional signals such as images. The efficient implementation on silicon of a complete processing chain for the signal via the approach using neural networks is provided. The circuit comprises at least: a series of neuro-blocks grouped together in branches composed of a group of neuro-blocks and a broadcasting bus, the neuro-blocks connected to the broadcasting bus; a routing unit connected to the broadcasting bus of the branches, carrying out the routing and broadcasting of data to and from the branches; a transformation module connected to the routing unit via an internal bus and designed to be connected at the input of the circuit to an external databus, the module carrying out the transformation of input data into serial coded data. The processing operations internal to the circuit are carried out according to a serial communications protocol.

First claim

The invention claimed is:

1. A circuit, comprising:
a series of neuro-blocks configured to implement a neural network, said neuro-blocks (i) each comprising a plurality of neurons and (ii) being grouped together in branches, each of the branches comprising a group of neuro-blocks and a broadcasting bus, the neuro-blocks being connected to said broadcasting buses;
a routing unit connected to the broadcasting buses of said branches and configured to route data to said branches; and
a transformation module connected to the routing unit via an internal bus and configured to be connected, at an input of said circuit, to an external bus, said module carrying out a transformation of a format of data inputted by said external bus, a first message of N input words with x bits coded in parallel being transformed into a second message of N words with x bits coded in series, the N words of the second message being parallelized over the internal bus at an output of said module, one wire of the internal bus being dedicated to each of the N transformed words, one bit of the each word being sequentially broadcast over the broadcasting buses of the branches via the routing unit at a time such that all processing operations of the series of the neuro-blocks are carried out according to a serial communications protocol,
wherein an inverse transformation is performed by the transformation module such that a third message of N words with the x bits coded in series is transformed into a fourth message of N output words with the x bits coded in parallel.

2. The circuit as claimed in claim 1 , wherein the routing unit comprises an input/output bus so as to route and to broadcast data to or from an external unit according to said serial communications protocol.

3. The circuit as claimed in claim 1 , wherein the communications protocol comprises, for the transmission of a given message, information indicating a target unit.

4. The circuit as claimed in claim 3 , wherein said information indicates an identifier of one or more neuro-blocks.

5. The circuit as claimed in claim 3 , wherein said information indicates one or more destination branches or an external unit for said given message.

6. The circuit as claimed in claim 1 , wherein the routing unit is further configured to perform global processing operations on data.

7. The circuit as claimed in claim 1 , further comprising:
a module for direct memory access (DMA) coupled via a bus to each neuro-block, said DMA module being configured to be interfaced with an external memory.

8. The circuit as claimed in claim 7 , further comprising:
a central control module, wherein said module for direct memory access is connected to said central control module via a bus.

9. The circuit as claimed in claim 1 , wherein the neuro-blocks each comprise a set of arithmetic and logic units, and
wherein all the arithmetic and logic units are connected to a same interconnection bus, said interconnection bus being configured to be extended outside of said circuit upstream and downstream of the neuro-blocks.

10. The circuit as claimed in claim 1 , wherein the broadcasting buses comprise available data wires.

11. The circuit as claimed in claim 1 , wherein the neuro-blocks are evenly divided in the groups.

12. The circuit as claimed in claim 1 , wherein it performs processing functions on a signal.

13. The circuit as claimed in claim 12 , wherein it performs pre-processing and/or post-processing functions on the signal with respect to neural processing functions.

14. A neural system, comprising several circuits as claimed in claim 1 .

15. The circuit as claimed in claim 1 , wherein a width of the external bus is equal to or greater than a number of bits per word, and wherein a width of the internal bus is equal to or greater than a number of words in the message.

16. The circuit as claimed in claim 1 , wherein said module further carries out a transformation of another format of data inputted by said internal bus, the data inputted by said internal bus having been routed, via the routing unit, from said branches.

17. The circuit as claimed in claim 1 , wherein the transformation allows for a reduction in a surface area of silicon for the circuit.

18. The circuit as claimed in claim 1 , wherein each of the neuro-blocks implements a node of the neural network.

19. The circuit as claimed in claim 1 , wherein a number of neuro-blocks is equal to the number N of the words.

20. The circuit as claimed in claim 1 , wherein the neuro-blocks are daisy-chained together.

21. The circuit as claimed in claim 1 , wherein a neuro-block of a branch exchanges data with other neuro-blocks of the same branch without interfering with neuro-blocks of another branch.

Assignees

• Commissariat Energie Atomique

Inventors

• Duranton Marc
• Philippe Jean-Marc
• Paindavoine Michel

Classifications

• G06N3/06 Primary

  Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons · CPC title

• G06N3/063 Primary

  using electronic means · CPC title