Method and device for predicting operation parameter of integrated circuit

Patent metadata

Field	Value
Publication number	US-11080445-B2
Application number	US-202016742160-A
Country	US
Kind code	B2
Filing date	Jan 14, 2020
Priority date	Sep 27, 2019
Publication date	Aug 3, 2021
Grant date	Aug 3, 2021

Abstract

A method for predicting an operation parameter of an integrated circuit includes the following steps. A plurality of cells used by the integrated circuit are provided. A voltage-frequency sweep test is performed on each of cells through a test model to generate a plurality of parameters, wherein the parameters correspond to a voltage value. A lookup table is established according to the parameters. A timing signoff corresponding to the integrated circuit is obtained. A timing analysis is performed on a plurality of timing paths of the integrated circuit according to the timing signoff and the parameters of the lookup table to obtain a critical timing path, and the operation parameter of the integrated circuit is predicted according to the critical timing path.

First claim

What is claimed is:

1. A method for predicting an operation parameter of an integrated circuit, comprising:
providing a plurality of cells used by the integrated circuit;
providing a test model comprising a first timing component and a second timing component, and configuring each of the cells to couple between the first timing component and the second timing component;
performing a voltage-frequency sweep test on each of the cells through the test model to obtain an operation time of each of the cells, and normalizing the operation time of each of the cells to generate a plurality of parameters, wherein the parameters correspond to a voltage value and the operation time is a time from an output terminal of the first timing component generating an output signal to an input terminal of the second timing component receiving an input signal;
establishing a lookup table according to the parameters;
obtaining a timing signoff corresponding to the integrated circuit; and
performing a timing analysis on a plurality of timing paths of the integrated circuit according to the timing signoff and the parameters of the lookup table to obtain a critical timing path, and predicting the operation parameter of the integrated circuit according to the critical timing path.

2. The method for predicting the operation parameter of the integrated circuit as claimed in claim 1 , wherein the step of performing the voltage-frequency sweep test on each of the cells through the test model to obtain the operation time of each of the cells, and normalizing the operation time of each of the cells to generate the plurality of parameters comprises:
performing the voltage-frequency sweep test on each of the cells through the test model in a plurality of different voltages to obtain the operation times of each of the cells, and normalizing the operation times of each of the cells to generate the plurality of parameters, wherein the parameters correspond to different voltage values.

3. The method for predicting the operation parameter of the integrated circuit as claimed in claim 2 , wherein the step of performing the timing analysis on the plurality of timing paths of the integrated circuit according to the timing signoff and the parameters of the lookup table to obtain the critical timing path, and predicting the operation parameter of the integrated circuit according to the critical timing path comprises:
multiplying a delay time of each of the cells used by the timing paths corresponding to the timing signoff by the corresponding parameter to obtain slack times of the timing paths corresponding to the different voltages;
selecting timing paths that the slack time is largest among the timing paths corresponding to the different voltages as the critical timing paths according to the slack times of the timing paths corresponding to the different voltages; and
predicting the operation parameters of the integrated circuit corresponding to the different voltages according to the slack times of the critical timing paths.

4. The method for predicting the operation parameter of the integrated circuit as claimed in claim 1 , wherein the step of performing the timing analysis on the plurality of timing paths of the integrated circuit according to the timing signoff and the parameters of the lookup table to obtain the critical timing path, and predicting the operation parameter of the integrated circuit according to the critical timing path comprises:
multiplying a delay time of each of the cells used by the timing paths corresponding to the timing signoff by the corresponding parameter to obtain slack times of the timing paths;
selecting one timing path that the slack time is largest among the timing paths as the critical timing path according to the slack times of the timing paths; and
predicting the operation parameter of the integrated circuit according to the slack time of the critical timing path.

5. The method for predicting the operation parameter of the integrated circuit as claimed in claim 1 , wherein the cells are all of the cells used by the timing paths of the integrated circuit, or cells used by the critical timing path of the integrated circuit.

6. A device for predicting an operation parameter of an integrated circuit, comprising:
a providing device, configured to provide a plurality of cells used by the integrated circuit;
a testing device, coupled to the providing device, and configured to obtain the cells, provide a test model comprising a first timing component and a second timing component and configure each of the cells to couple between the first timing component and the second timing component, and perform a voltage-frequency sweep test on each of the cells through the test model to obtain an operation time of each of the cells and normalize the operation time of each of the cells to generate a plurality of parameters, wherein the parameters correspond to a voltage value and the operation time is a time from an output terminal of the first timing component generating an output signal to an input terminal of the second timing component receiving an input signal;
a processing device, coupled to the testing device, and configured to obtain the parameters, establish a lookup table according to the parameters, obtain a timing signoff corresponding to the integrated circuit, perform a timing analysis on a plurality of timing paths of the integrated circuit according to the timing signoff and the parameters of the lookup table to obtain a critical timing path, and predict the operation parameter of the integrated circuit according to the critical timing path.

7. The device for predicting the operation parameter of the integrated circuit as claimed in claim 6 , further comprising a storage unit, configured to store the lookup table.

8. The device for predicting the operation parameter of the integrated circuit as claimed in claim 6 , wherein the testing device performs the voltage-frequency sweep test on each of the cells through the test model in a plurality of different voltages to obtain the operation times of each of the cells, and normalizes the operation times of each of the cells to generate the plurality of parameters, wherein the parameters correspond to different voltage values.

9. The device for predicting the operation parameter of the integrated circuit as claimed in claim 8 , wherein the processing device multiplies a delay time of each of the cells used by the timing paths corresponding to the timing signoff by the corresponding parameter to obtain slack times of the timing paths corresponding to the different voltages, the processing device selects timing paths that the slack time is largest among the timing paths corresponding to the different voltages as the critical timing paths according to the slack times of the timing paths corresponding to the different voltages, and the processing device predicts the operation parameters of the integrated circuit corresponding to the different voltages according to the slack times of the critical timing paths.

10. The device for predicting the operation parameter of the integrated circuit as claimed in claim 6 , wherein the processing device multiplies a delay time of each of the cells used by the timing paths corresponding to the timing signoff by the corresponding parameter to obtain slack times of the timing paths, selects one timing path that the slack time is largest among the timing paths as the critical timing path according to the slack times of the timing paths, and predicts the operation parameter of the integrated circuit according to the slack time of the critical timing path.

11. The device for predicting the operation parameter of the integrated circ

Assignees

• Shanghai Zhaoxin Semiconductor Co Ltd

Inventors

• Li Yi
• Li Xiaojing
• Liu Miao

Classifications

• G06F30/3312 Primary

  Timing analysis · CPC title

• G01R31/30

  Marginal testing, e.g. by varying supply voltage (testing computers during standby operation or idle time G06F11/22) · CPC title

• G06F30/367

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• G01R31/31725

  Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937) · CPC title

• G01R31/3016 Primary

  Delay or race condition test, e.g. race hazard test · CPC title