Dynamic presentation of interconnect protocol capability structures

Patent metadata

Field	Value
Publication number	US-11080223-B2
Application number	US-201916513941-A
Country	US
Kind code	B2
Filing date	Jul 17, 2019
Priority date	Jul 17, 2019
Publication date	Aug 3, 2021
Grant date	Aug 3, 2021

Abstract

A device connected by a link to a host system can include a first port to receive a capability configuration message across a link and a message request receiving logic comprising hardware circuitry to identify a capability of the device identified in the capability configuration message, determine that the capability is to be presented or hidden from operation based on a capability hide enable bit in the capability configuration message, and configure a capability linked list to present or hide the capability based on the determination. The device can also include a message response generator logic comprising hardware circuitry to generate a response message indicating that the capability is to be presented or hidden from operation. The device can include a second port to transmit the response message across the link.

First claim

What is claimed is:

1. An apparatus comprising:
a first port to receive a capability configuration message from a device connected across a link;
a message request receiving logic comprising hardware circuitry to:
identify a capability of the device identified in the capability configuration message,
determine that the capability is to be presented or hidden from operation based on a capability hide enable bit in the capability configuration message, and
configure a capability linked list of the apparatus to present or hide the capability in subsequent capability exploration requests based on the determination;

a message response generator logic comprising hardware circuitry to generate a response message indicating that the capability is to be presented or hidden from operation; and
a second port to transmit the response message across the link.

2. The apparatus of claim 1 , wherein the capability configuration message or the response message comprises a transaction layer packet (TLP) based on a Peripheral Component Interconnect Express (PCIe) protocol.

3. The apparatus of claim 2 , wherein the capability configuration message or the response message comprises a vendor-defined message (VDM) transaction layer packet.

4. The apparatus of claim 1 , wherein the capability configuration message comprises a capability structure configuration request message identifying capability of the apparatus to present or to hide.

5. The apparatus of claim 1 , further comprising a capability pointer switch logic to update a next capability field in the capability linked list.

6. The apparatus of claim 5 , wherein the capability linked list comprises a capability identifier and a next capability pointer, the capability identifier indicating an identifier for each capability and the next capability pointer pointing to a next capability in the capability linked list.

7. The apparatus of claim 1 , the message request receiving logic to identify for the apparatus a mapping between a capability and a corresponding capability index from a capability structure table; and
the response message generator logic to compose a response message indicating the mapping between the capability and the corresponding capability index.

8. The apparatus of claim 6 , the message request receiving logic to:
receive a capability configuration initialization request message;
extract capability structure configuration information from the capability configuration initialization request message; and
update the capability structure table with the capability structure configuration information.

9. A method comprising:
receiving, at a first device, a capability configuration message from a second device;
identifying a capability of the first device identified in the capability configuration message;
determining that the capability is to be presented or hidden from operation based on a capability hide enable bit in the capability configuration message;
configuring a capability linked list of the first device to present or hide the capability in subsequent capability exploration requests based on the determination;
generating a response message indicating that the capability is to be presented or hidden from operation; and
transmitting the response message across a link.

10. The method of claim 9 , further comprising updating, by a capability pointer switch logic, a next capability field in the capability linked list.

11. The method of claim 10 , further comprising updating a capability identifier and a next capability pointer of the capability linked list, the capability identifier indicating an identifier for each capability and the next capability pointer pointing to a next capability in the capability linked list.

12. The method of claim 9 , further comprising:
identifying a mapping between a capability and a corresponding capability index from a capability structure table;
composing a response message indicating the mapping between the capability and the corresponding capability index;
receiving a capability configuration initialization request message;
extracting capability structure configuration information from the capability configuration initialization request message; and

updating the capability structure table with the capability structure configuration information.

13. The apparatus of claim 1 , wherein the capability configuration message is associated with a first requester entity of the device, and the message request receiving logic is further to configure the capability linked list to hide the capability from a second requester entity of the device.

14. The method of claim 9 , wherein the capability configuration message is associated with a first requester entity of the second device, and the capability linked list is configured to hide the capability from a second requester entity of the second device.

Assignees

• Intel Corp

Inventors

• Tan Kuan Hua
• Ooi Eng Hun
• Li Ang

Classifications

• G06F9/44505

  Configuring for program initiating, e.g. using registry, configuration files · CPC title

• G06F13/4221 Primary

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F2213/0026

  PCI express · CPC title