Addition instructions with independent carry chains

Patent metadata

Field	Value
Publication number	US-11080045-B2
Application number	US-201113993483-A
Country	US
Kind code	B2
Filing date	Dec 22, 2011
Priority date	Dec 22, 2011
Publication date	Aug 3, 2021
Grant date	Aug 3, 2021

Abstract

A number of addition instructions are provided that have no data dependency between each other. A first addition instruction stores its carry output in a first flag of a flags register without modifying a second flag in the flags register. A second addition instruction stores its carry output in the second flag of the flags register without modifying the first flag in the flags register.

First claim

What is claimed is:

1. A method performed by a processor comprising a multi-bit flags register having a plurality of arithmetic flag bits, the method comprising:
fetching, using instruction fetch circuitry, first and second addition instructions;
decoding, using decode circuitry, the first and second addition instructions, wherein the first and second addition instructions have opcodes specifying, respectively, different first and second flag bits, of the plurality of arithmetic flag bits, from which to read a respective carry-in of the first and second addition instructions and to which to write a respective carry-out of the first and second addition instructions; and
executing, using execution circuitry, the first and second addition instructions in parallel, writing carry-outs to the first and second flag bits, without writing to other flag bits.

2. The method of claim 1 , further comprising clearing the plurality of arithmetic flag bits by using the instruction fetch circuitry, the decode circuitry, and the execution circuitry to fetch, decode, and execute an XOR instruction.

3. The method of claim 1 , wherein the plurality of arithmetic flag bits comprises a carry flag, an overflow flag, a sign flag, a parity flag, an auxiliary carry flag, and a zero flag.

4. The method of claim 1 , further comprising fetching and decoding a subtraction instruction specifying a third flag bit of the plurality of arithmetic flag bits, and executing the subtraction instruction to read the third flag bit as a borrow input, and to write a borrow output into the third flag bit without writing to other flag bits.

5. The method of claim 1 , further comprising fetching, decoding, and executing a multiplication instruction to multiply a first factor with a second factor to produce a product that includes a least significant half and a most significant half, the least significant half being a source operand for the first addition instruction, and the most significant half being a source operand for the second addition instruction.

6. The method of claim 5 , wherein the first and second factors are each 64 bits wide, and the product is 128 bits wide.

7. A processor comprising:
a multi-bit flags register having a plurality of arithmetic flag bits;
fetch circuitry to fetch first and second addition instructions;
decode circuitry to decode the first and second addition instructions, wherein the first and second addition instructions have opcodes specifying, respectively, different first and second flag bits, of the plurality of arithmetic flag bits, from which to read a respective carry-in of the first and second addition instructions and to which to write a respective carry-out of the first and second addition instructions; and
execution circuitry to execute the first and second addition instructions in parallel, writing carry-outs to the first and second flag bits, without writing to other flag bits.

8. The processor of claim 7 , wherein the fetch circuitry, the decode circuitry, and the execution circuitry are further to clear the plurality of arithmetic flag bits by fetching, decoding, and executing an XOR instruction.

9. The processor of claim 7 , wherein the plurality of arithmetic flag bits comprises a carry flag, an overflow flag, a sign flag, a parity flag, an auxiliary carry flag, and a zero flag.

10. The processor of claim 7 , wherein the fetch circuitry and the decode circuitry are further to fetch and decode a subtraction instruction specifying a third flag bit of the plurality of arithmetic flag bits, and wherein the execution circuitry is further to execute the subtraction instruction to read the third flag bit as a borrow input, and to write a borrow output into the third flag bit without writing to other flag bits.

11. The processor of claim 7 , wherein the fetch circuitry, the decode circuitry, and the execution circuitry are further to fetch, decode, and execute a multiplication instruction to multiply a first factor with a second factor to produce a product that includes a least significant half and a most significant half, the least significant half being a source operand for the first addition instruction, and the most significant half being a source operand for the second addition instruction.

12. The processor of claim 11 , wherein the first and second factors are each 64 bits wide, and the product is 128 bits wide.

13. A non-transitory machine-readable medium containing code, that when executed, causes a processor comprising a multi-bit flags register having a plurality of arithmetic flag bits to perform operations comprising:
fetching, using instruction fetch circuitry, first and second addition instructions;
decoding, using decode circuitry, the first and second addition instructions, wherein the first and second addition instructions have opcodes specifying, respectively, different first and second flag bits, of the plurality of arithmetic flag bits, from which to read a respective carry-in of the first and second addition instructions and to which to write a respective carry-out of the first and second addition instructions; and
executing, using execution circuitry, the first and second addition instructions in parallel, writing carry-outs-to the first and second flag bits, without writing to other flag bits.

14. The non-transitory machine-readable medium of claim 13 , wherein the operations further comprise clearing the plurality of arithmetic flag bits by using the instruction fetch circuitry, the decode circuitry, and the execution circuitry to fetch, decode, and execute an XOR instruction.

15. The non-transitory machine-readable medium of claim 13 , wherein the plurality of arithmetic flag bits comprises a carry flag, an overflow flag, a sign flag, a parity flag, an auxiliary carry flag, and a zero flag.

16. The non-transitory machine-readable medium of claim 13 , wherein the operations further comprise fetching and decoding a subtraction instruction specifying a third flag bit of the plurality of arithmetic flag bits, and executing the subtraction instruction to read the third flag bit as a borrow input, and to write a borrow output into the third flag bit without writing to other flag bits.

Assignees

• Gopal Vinodh
• Guilford James D
• Wolrich Gilbert M
• Feghali Wajdi K
• Ozturk Erdinc
• Dixon Martin G
• Mirkes Sean P
• Merten Matthew C
• Li Tong
• Toll I Bret T
• Intel Corp

Inventors

• Gopal Vinodh
• Guilford James D
• Wolrich Gilbert M
• Feghali Wajdi K
• Ozturk Erdinc
• Dixon Martin G
• Mirkes Sean P
• Merten Matthew C
• Li Tong
• Toll I Bret T

Classifications

• G06F9/3838

  Dependency mechanisms, e.g. register scoreboarding · CPC title

• G06F9/30094 Primary

  Condition code generation, e.g. Carry, Zero flag · CPC title

• G06F9/3001 Primary

  Arithmetic instructions · CPC title