Apparatus and method for reducing di/dt

Patent metadata

Field	Value
Publication number	US-11079830-B2
Application number	US-201615163494-A
Country	US
Kind code	B2
Filing date	May 24, 2016
Priority date	May 24, 2016
Publication date	Aug 3, 2021
Grant date	Aug 3, 2021

Abstract

Described is an apparatus which comprises: a controllable power gate coupled to an ungated power supply node and a gated power supply node; and a charge-pump circuit operable to be turned on and off according to a logic, wherein the charge pump circuit is coupled in parallel to the controllable power gate and also coupled to the ungated power supply node and the gated power supply node.

First claim

We claim:

1. An apparatus comprising:
a controllable power gate coupled to an ungated power supply node and a gated power supply node;
a charge-pump circuit operable to be turned on and off according to a logic, wherein the charge-pump circuit is coupled in parallel to the controllable power gate and also coupled to the ungated power supply node and the gated power supply node, wherein the charge-pump circuit has substantially constant charge transfer efficiency; and
a transistor controllable by a low power mode signal, wherein the transistor is coupled in series with the charge-pump circuit such that the transistor and the charge-pump circuit together are coupled in parallel to the controllable power gate.

2. The apparatus of claim 1 , wherein the charge-pump circuit is operable to turn on such that the gated power supply node is charged faster than when the charge-pump circuit is off.

3. The apparatus of claim 1 , wherein the charge-pump circuit is operable to provide a constant current to the gated power supply node.

4. The apparatus of claim 1 , wherein the charge-pump circuit is operable to turn off for at least two clock cycles.

5. The apparatus of claim 1 , wherein the logic is to count edges of a clock and to generate a pulse to turn off the charge-pump circuit.

6. The apparatus of claim 1 , wherein the charge-pump circuit comprises a multi-phase charge-pump.

7. The apparatus of claim 1 , wherein the controllable power gate comprises a primary power gate and a secondary power gate, wherein the primary power gate is larger than the secondary power gate.

8. The apparatus of claim 7 , wherein the primary power gate comprises two or more transistors which are operable to turn on sequentially.

9. The apparatus of claim 8 , wherein the secondary power gate comprises two or more transistors which are to turn on after at least one transistor of the primary power gate is turned on.

10. The apparatus of claim 9 , wherein the two or more transistors of the secondary power gate are configured in a daisy chain.

11. An apparatus comprising:
an ungated power supply node;
a gated power supply node;
a primary power gate coupled to the ungated power supply node and the gated power supply node;
a secondary power gate coupled to the ungated power supply node and the gated power supply node, the secondary power gate being smaller in size than the primary power gate, wherein the primary power gate and the secondary power gate have a same conductivity type;
logic to generate a pulse; and
a charge-pump circuit operable to be turned on and off according to the pulse, wherein the charge-pump circuit is coupled in parallel to a controllable power gate and also coupled to the ungated power supply node and the gated power supply node, and wherein the charge-pump circuit has substantially constant charge transfer efficiency.

12. The apparatus of claim 11 , wherein the charge-pump circuit is operable to provide a constant current to the gated power supply node.

13. The apparatus of claim 11 , wherein the logic is to generate a first edge of the pulse after at least one clock cycle.

14. The apparatus of claim 11 , wherein the charge-pump circuit is to be turned off after the primary power gate is turned on.

15. The apparatus of claim 11 , wherein the charge-pump circuit is a multi-phase charge-pump circuit.

16. A system comprising:
a memory;
a processor coupled to the memory, the processor including:
a controllable power gate coupled to an ungated power supply node and a gated power supply node;
a charge-pump circuit operable to be turned on and off according to a logic, wherein the charge pump circuit is coupled in parallel to the controllable power gate and also coupled to the ungated power supply node and the gated power supply node, wherein the charge-pump circuit has substantially constant charge transfer efficiency; and
a transistor controllable by a low power mode signal, wherein the transistor is coupled in series with the charge-pump circuit such that the transistor and the charge-pump circuit together are coupled in parallel to the controllable power gate; and

a wireless interface to allow the processor to communicate with another device.

17. The system of claim 16 , wherein the charge-pump circuit is operable to turn on such that the gated power supply node is charged faster than when the charge-pump circuit is off.

18. The system of claim 16 , wherein the charge-pump circuit is operable to provide a constant current to the gated power supply node.

19. The system of claim 16 , wherein the charge-pump circuit is operable to turn off for at least two clock cycles.

20. The system of claim 16 , wherein the logic is to count edges of a clock and to generate a pulse to turn off the charge-pump circuit.

21. An apparatus comprising:
a controllable power gate coupled to an ungated power supply node and a gated power supply node;
a charge-pump coupled to the controllable power gate;
a logic to turn on the charge pump when the controllable power gate is just turned on, and to turn off the charge pump during a voltage droop on the gated power supply node; and
a transistor controllable by a low power mode signal, wherein the transistor is coupled in series with the charge-pump such that the transistor and the charge-pump together are coupled in parallel to the controllable power gate.

22. The apparatus of claim 21 , wherein the logic is to turn on the charge-pump after a current peak on the ungated power supply node passes.

23. The apparatus of claim 21 , wherein the logic is to turn on the charge-pump after a peak of the voltage droop passes.

24. The apparatus of claim 21 , wherein the logic comprises a finite state machine.

25. The apparatus of claim 21 , wherein the logic is to monitor a current level from the charge-pump to generate a pulse to turn off the charge-pump.

26. The apparatus of claim 21 , wherein an effective resistance of the charge-pump and the transistor is greater than an effective resistance of the controllable power gate.

Assignees

• Intel Corp

Inventors

• Kulkarni Jaydeep P
• Shim Yong
• Meinerzhagen Pascal A

Classifications

• G06F1/3287 Primary

  by switching off individual functional units in the computer system · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F1/324 Primary

  by lowering clock frequency · CPC title

• H02M3/07

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title