Array substrate and fabricating method thereof, reflective display panel, and display device

Patent metadata

Field	Value
Publication number	US-11079621-B2
Application number	US-201916538438-A
Country	US
Kind code	B2
Filing date	Aug 12, 2019
Priority date	Jan 7, 2019
Publication date	Aug 3, 2021
Grant date	Aug 3, 2021

Abstract

The present disclosure provides an array substrate. The array substrate includes a base on which pixel electrodes, gate lines, data lines, and thin film transistors are disposed. The data lines and the gate lines are alternately arranged to define a plurality of pixel units one-to-one corresponding to the pixel electrodes and the thin film transistors. An insulating layer is disposed between the pixel electrodes and a layer where a data pattern is located. The data pattern, part of which is overlapped with the pixel electrodes, includes the data lines and source electrodes of the thin film transistors. The insulating layer is provided with recesses, and an orthographic projection of the recess on the base is outside of an orthographic projection of an overlapping region of the pixel electrode and the data pattern on the base.

First claim

What is claimed is:

1. An array substrate, comprising:
a base on which pixel electrodes, gate lines, data lines, and thin film transistors are disposed, the data lines and the gate lines being alternately arranged to define a plurality of pixel units, and both the pixel electrodes and the thin film transistors being in one-to-one correspondence with the pixel units;
an insulating layer disposed between the pixel electrodes and a layer where a data pattern is located, wherein the data pattern comprises the data lines and source electrodes of the thin film transistors, the pixel electrodes overlap with a portion of the data pattern, the pixel electrodes are connected to drain electrodes of the thin film transistors through via holes, and the pixel electrodes overlap at least part of each of the data lines and overlap the drain electrodes and the source electrodes;
a plurality of recesses disposed on the insulating layer, wherein an orthographic projection of one of the recesses on the base is outside of an orthographic projection of an overlapping region of one of the pixel electrodes and the data pattern on the base; and
wherein a row spacing region exists between every two adjacent rows of pixel electrodes, a column spacing region exists between every adjacent two columns of pixel electrodes, a cross region of the row spacing region and the column spacing region is a spacer region, and an orthographic projection of the spacer region does not overlap with orthographic projections of the data lines and the gate lines.

2. The array substrate according to claim 1 , wherein the one of the pixel electrodes overlaps with a portion of one of the data lines.

3. The array substrate according to claim 1 , wherein the orthographic projection of the one of the recesses on the base does not overlap with an orthographic projection of one of the data lines on the base.

4. The array substrate according to claim 1 , wherein the orthographic projection of the one of the recesses on the base is outside of an orthographic projection of one of the thin film transistors on the base.

5. The array substrate according to claim 1 , wherein each of the pixel electrodes is a reflective electrode.

6. The array substrate according to claim 1 , wherein:
the orthographic projection of one of the recesses on the base is outside of an orthographic projection of at least a portion of the spacer region on the base.

7. The array substrate according to claim 1 , wherein the array substrate is part of a reflective display panel, the reflective display panel comprising the array substrate, a cell substrate, and a liquid crystal layer between the array substrate and the cell substrate.

8. The array substrate according to claim 7 , wherein each of the pixel electrodes is a reflective electrode, and each of the recesses on the insulating layer is configured such that: light having an angle between 25° and 35° with respect to a thickness direction of the reflective display panel is incident on the reflective display panel, and then is reflected by one of the pixel electrodes in the thickness direction of the reflective display panel.

9. The array substrate according to claim 7 , wherein each of the recesses has a slope angle between 9° and 12°, and the slope angle is an angle between a cut surface at a midpoint of a bottom end and a top end of a sidewall of the recess, and a display surface of the reflective display panel.

10. The array substrate according to claim 7 , wherein the reflective display panel is part of a display device.

11. The array substrate according to claim 10 , wherein each of the pixel electrodes is a reflective electrode, and each of the recesses on the insulating layer is configured such that: light having an angle between 25° and 35° with respect to a thickness direction of the reflective display panel is incident on the reflective display panel, and then is reflected by one of the pixel electrodes in the thickness direction of the reflective display panel.

12. The array substrate according to claim 10 , wherein each of the recesses has a slope angle between 9° and 12°, and the slope angle is an angle between a cut surface at a midpoint of a bottom end and a top end of a sidewall of the recess, and a display surface of the reflective display panel.

13. A method of fabricating the array substrate according to claim 1 , comprising:
forming a pattern comprising gate lines on the base;
forming a data pattern, the data pattern comprising data lines and source electrodes of thin film transistors, and the gate lines and the data lines are alternately arranged to define a plurality of pixel units;
forming an insulating layer;
forming a plurality of recesses on the insulating layer; and
forming a pattern including pixel electrodes, the pixel electrodes overlapping with a portion of the data pattern, and an orthographic projection of one of the recesses on the base being outside of an orthographic projection of an overlapping region of one of the pixel electrodes and the data pattern on the base.

14. The method according to claim 13 , wherein the insulating layer is made of photoresist, and the insulating layer comprises a first region, a second region, and a third region outside of the first region and the second region, the first region being a region where a via hole is to be formed, and the second region being a region where the one of the recesses is to be formed;
forming the plurality of recesses on the insulating layer comprises:
exposing the insulating layer by using a mask plate, wherein the mask plate comprises a transmitting region, a semi-transmitting region and a non-transmitting region, when the insulating layer is made of a positive photoresist, the transmitting region of the mask plate corresponding to the first region, the semi-transmitting region of the mask plate corresponding to the second region, and the non-transmitting region of the mask plate corresponding to the third region, and when the insulating layer is made of a negative photoresist, the non-transmitting region of the mask plate corresponding to the first region, the semi-transmitting region of the mask plate corresponding to the second region, and the transmitting region of the mask plate corresponding to the third region; and
developing the exposed insulating layer to form the via hole and the plurality of recesses.

15. A display device comprising a reflective display panel, the reflective display panel comprising:
an array substrate, a cell substrate, and a liquid crystal layer between the array substrate and the cell substrate, wherein the array substrate comprises:
a base having a plurality of pixel electrodes, a plurality of gate lines, a plurality of data lines, and a plurality of thin film transistors disposed thereon, wherein the data lines and the gate lines are alternately arranged to provide a plurality of pixel units, and both the pixel electrodes and the thin film transistors are in a one-to-one correspondence with the pixel units;
an insulating layer disposed between the pixel electrodes and a layer where a data pattern is located, wherein the data pattern comprises the data lines and source electrodes of the thin film transistors, the pixel electrodes overlap with a portion of the data pattern, the pixel electrodes are connected to drain electrodes of the thin film transistors through via holes, and the pixel electrodes overlap at least part of each of the data lines and overlap the drain electrodes and the source electrodes;
a plurality of recesses disposed on the insulating layer, wherein an orthographic projection of one of the recesses on t

Assignees

• Beijing Boe Optoelectronics Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Zheng Qi
• Bai Lu
• Hua Gang
• Yuan Hongliang
• Li Peng
• Lv Xiaohui

Classifications

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/451 Primary

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/0231

  using masks, e.g. half-tone masks · CPC title

• H10D86/0251

  characterised by increasing the uniformity of device parameters · CPC title