Semiconductor device and manufacturing method of the same

Patent metadata

Field	Value
Publication number	US-11079539-B2
Application number	US-201916370409-A
Country	US
Kind code	B2
Filing date	Mar 29, 2019
Priority date	Apr 16, 2018
Publication date	Aug 3, 2021
Grant date	Aug 3, 2021

Abstract

According to the present invention, a first semiconductor chip includes a semiconductor substrate, an optical waveguide formed on an upper surface of the semiconductor substrate, and a concave portion formed in the semiconductor substrate in a region that differs from a region in which the optical waveguide is formed. A second semiconductor chip includes a compound semiconductor substrate, and a light emitting unit formed on an upper surface of the compound semiconductor substrate and emitting a laser beam. The second semiconductor chip is mounted in the concave portion of the first semiconductor chip, and a pedestal which is an insulating film is formed between a bottom surface of the concave portion and a back surface of the compound semiconductor substrate.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first semiconductor chip that includes:
a first substrate;
an insulating layer formed on an upper surface of the first substrate;
an optical waveguide formed on the insulating layer;
an interlayer insulating film formed over the insulating layer so as to cover the optical waveguide; and
a concave portion formed in a region of the first substrate different from a region in which the optical waveguide is formed,
wherein the concave portion penetrates into the first substrate through the interlayer insulating film and the insulating layer; and

a second semiconductor chip that includes a second substrate, and a light emitting unit formed on an upper surface of the second substrate and emitting a light toward the optical waveguide,
wherein the second semiconductor chip is mounted in the concave portion, and
wherein a pedestal which is an insulating film is formed between a bottom surface of the concave portion and a back surface of the second substrate, the back surface being a surface opposite to the upper surface of the second substrate.

2. The semiconductor device according to claim 1 ,
wherein the optical waveguide extends in a first direction in plan view and includes a first end surface in the first direction,
the light emitting unit extends in the first direction in plan view and includes a second end surface in the first direction, and
the second end surface of the light emitting unit faces the first end surface of the optical waveguide.

3. The semiconductor device according to claim 1 ,
wherein a first electrode is formed on the bottom surface of the concave portion,
a second electrode is formed on the back surface of the second substrate,
the first electrode is electrically connected to the second electrode via a bump electrode, and
the bump electrode is formed at a position not overlapping the pedestal in plan view.

4. The semiconductor device according to claim 3 , wherein the pedestal is adhered to the second electrode.

5. The semiconductor device according to claim 1 , wherein three or more pedestals are formed.

6. The semiconductor device according to claim 5 , wherein, when three or more virtual lines connecting each center of the three or more pedestals to one another in plan view are drawn, a polygonal shape is formed by the three or more virtual lines.

7. The semiconductor device according to claim 6 ,
wherein the second semiconductor chip includes a first side and a second side opposite to each other in a first direction in plan view, and a third side and a fourth side opposite to each other in a second direction orthogonal to the first direction in plan view, and
wherein one or more pedestals are arranged at positions closer to the first side than to a first center line connecting a center point of the third side and a center point of the fourth side to each other in plan view, and one or more pedestals are arranged at positions closer to the second side than to the first center line in plan view.

8. The semiconductor device according to claim 7 , wherein one or more pedestals are arranged at positions closer to the third side than to a second center line connecting a center point of the first side and a center point of the second side to each other in plan view, and one or more pedestals are arranged at positions closer to the fourth side than to the second center line in plan view.

9. The semiconductor device according to claim 7 , wherein, when the number of pedestals arranged at positions closer to the first side than to the first center line in plan view and the number of pedestals arranged at positions closer to the second side than to the first center line in plan view differ from each other, a planar area of the pedestal among the fewer number of pedestals is greater than a planar area of the pedestal among the larger number of pedestals.

10. The semiconductor device according to claim 5 , wherein a planar shape of each of the three or more pedestals is a circle or an ellipse.

11. The semiconductor device according to claim 5 , wherein a planar shape of each of the three or more pedestals is a regular hexagon.

Assignees

• Renesas Electronics Corp

Inventors

• Iida Tetsuya
• Nakashiba Yasutaka

Classifications

• H10F77/933

  for devices having potential barriers · CPC title

• H10F77/413

  directly associated or integrated with the devices, e.g. back reflectors (directly associated or integrated with photovoltaic cells H10F77/42) · CPC title

• H10F71/00

  Manufacture or treatment of devices covered by this subclass (patterning processes to connect thin photovoltaic cells in integrated devices, or assemblies of multiple devices, having photovoltaic cells H10F19/33; manufacture or treatment of encapsulations or containers for integrated devices, or assemblies of multiple devices, having photovoltaic cells H10F19/80; manufacture or treatment of integrated devices, or assemblies of multiple devices, comprising at least one element in which radiation controls the flow of current H10F39/00) · CPC title

• H10F55/00

  Radiation-sensitive semiconductor devices covered by groups H10F10/00, H10F19/00 or H10F30/00 being structurally associated with electric light sources and electrically or optically coupled thereto · CPC title

• H01S5/02326 Primary

  Arrangements for relative positioning of laser diodes and optical components, e.g. grooves in the mount to fix optical fibres or lenses · CPC title