Peak detector calibration

US11079415B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11079415-B2
Application numberUS-201916520978-A
CountryUS
Kind codeB2
Filing dateJul 24, 2019
Priority dateJul 24, 2019
Publication dateAug 3, 2021
Grant dateAug 3, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A calibration circuit for calibrating a peak detector configured to detect a signal peak amplitude of an oscillator, including: a calibration oscillator configured to be supplied by at least two different supply voltages to generate respective calibration signals; a calibration peak detector configured to detect a calibration signal peak amplitude of each of the calibration signals; and a logic circuit configured to calibrate the peak detector based on the detected calibration signal peak amplitudes.

First claim

Opening claim text (preview).

What is claimed is: 1. A calibration circuit for calibrating a peak detector configured to detect a signal peak amplitude of an oscillator, comprising: a calibration oscillator configured to be supplied by at least two different supply voltages to generate respective calibration signals; a calibration peak detector configured to detect a calibration signal peak amplitude of each of the calibration signals; and a logic circuit configured to calibrate the peak detector based on the detected calibration signal peak amplitudes. 2. The calibration circuit of claim 1 , wherein the logic circuit is configured to determine a gain of the calibration peak detector based on an interpolation of the detected calibration signal peak amplitudes, and calibrate the peak detector based on the determined gain. 3. The calibration circuit of claim 1 , further comprising: an analog-to-digital converter configured to sample and convert outputs of the calibration peak detector and the peak detector and provide the sampled and converted outputs to the logic circuit. 4. The calibration circuit of claim 1 , wherein the calibration peak detector is a replica of the peak detector. 5. The calibration circuit of claim 1 , wherein the calibration oscillator is an inductor capacitor based oscillator. 6. The calibration circuit of claim 1 , further comprising: a supply voltage regulator configured to generate the at least two different supply voltages. 7. The calibration circuit of claim 6 , wherein the supply voltage regulator is configured to supply the calibration oscillator with two different supply voltages to derive a linear transfer function of a gain of the calibration peak detector. 8. The calibration circuit of claim 6 , wherein the supply voltage regulator is configured to supply the calibration oscillator with more than two different supply voltages to derive a nonlinear transfer function of a gain of the calibration peak detector. 9. The calibration circuit of claim 1 , further comprising: a memory comprising a lookup table configured to store the detected calibration signal peak amplitudes. 10. The calibration circuit of claim 1 , wherein the oscillator and the calibration oscillator are of different oscillator types. 11. The calibration circuit of claim 1 , wherein the calibration oscillator comprises a Complementary Metal Oxide Semiconductor (CMOS) oscillator, an inductor capacitor based oscillator, or a ring oscillator. 12. The calibration circuit of claim 1 , wherein the logic circuit is configured to adjust a control word of a programmable current source of the oscillator to control the signal peak amplitude of the oscillator. 13. An oscillator circuit, comprising: an oscillator configured to generate a signal; a peak detector configured to detect a signal peak amplitude of a signal of the oscillator; a supply voltage regulator configured to generate at least two different supply voltages; a calibration oscillator configured to be supplied by the at least two different supply voltages to generate respective calibration signals; a calibration peak detector configured to detect a calibration signal peak amplitude of each of the calibration signals; and a logic circuit configured to determine a gain of the calibration peak detector based on an interpolation of the detected calibration signal peak amplitudes, and calibrate the oscillator through the peak detector based on the determined gain. 14. The oscillator circuit of claim 13 , wherein the oscillator, the peak detector, the calibration oscillator and the calibration peak detector are integrated on a same semiconductor chip. 15. The oscillator circuit of claim 13 , further comprising: an analog-to-digital converter configured to sample and convert outputs of the calibration peak detector and the peak detector and provide the sampled and converted outputs to the logic circuit. 16. The oscillator circuit of claim 13 , further comprising: a programmable current source configured to supply current to the oscillator, wherein the logic circuit is configured to adjust a control word of the programmable current source based on the detected signal peak amplitude of the oscillator. 17. A calibration method for calibrating a peak detector configured to detect a signal peak amplitude of an oscillator, the calibration method comprising: generating at least two different supply voltages; generating, by a calibration oscillator supplied by the at least two different supply voltages, respective calibration signals; detecting a calibration signal peak amplitude of each of the calibration signals; and calibrating the peak detector based on the detected calibration signal peak amplitudes. 18. The calibration method of claim 17 , further comprising: sampling and converting outputs of the calibration peak detector. 19. The calibration method of claim 17 , further comprising: supplying the calibration oscillator with more than two different supply voltages; and deriving a nonlinear transfer function of a gain of a calibration peak detector. 20. The calibration method of claim 17 , further comprising: adjusting a control word of a programmable current source of the oscillator to control the signal peak amplitude of the oscillator.

Assignees

Inventors

Classifications

  • the frequency being controlled by a control current, i.e. current controlled oscillators · CPC title

  • G01R19/04Primary

    Measuring peak values {or amplitude or envelope} of AC or of pulses · CPC title

  • the parameter being an amplitude of a signal, e.g. maintaining a constant output amplitude over the frequency range · CPC title

  • Calibrating; Standards or reference devices, e.g. voltage or resistance standards, "golden" references (G01R33/0035, G01R35/002 take precedence) · CPC title

  • and comprising means for varying the output amplitude of the generator (H03B5/1278 takes precedence) · CPC title

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What does patent US11079415B2 cover?
A calibration circuit for calibrating a peak detector configured to detect a signal peak amplitude of an oscillator, including: a calibration oscillator configured to be supplied by at least two different supply voltages to generate respective calibration signals; a calibration peak detector configured to detect a calibration signal peak amplitude of each of the calibration signals; and a logic…
Who is the assignee on this patent?
Infineon Technologies Ag
What technology area does this patent fall under?
Primary CPC classification G01R19/04. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Aug 03 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).