Self-processing synthesis of hybrid nanostructures

Patent metadata

Field	Value
Publication number	US-11078073-B2
Application number	US-201615551408-A
Country	US
Kind code	B2
Filing date	Apr 21, 2016
Priority date	Feb 23, 2015
Publication date	Aug 3, 2021
Grant date	Aug 3, 2021

Abstract

Provided is a self-processing synthesis of hybrid nanostructures, novel nanostructures and uses thereof in the construction of electronic and optoelectronic devices.

First claim

The invention claimed is:

1. A process for patterning a nanostructure consisting of a first metal and a semiconductor material with an oxide layer on the semiconductor material, said patterning being at a metal-semiconductor junction of the first metal and the semiconductor material, wherein the first metal is in direct contact with a surface of the semiconductor material, and wherein a portion of the semi-conductor material with the oxide layer thereon is at a region of the nanostructure at a vicinity of the junction,
the process comprising:
contacting said nanostructure in solution with a processing solution comprising at least one etchant, at least one reducing agent and at least one metal source of a second metal, wherein said contacting of said nanostructure in solution with the processing solution comprises immersing the nanostructure in the processing solution; and
said contacting of the nanostructure causing self-processing involving selective etching of the oxide layer solely at said region at the vicinity of the junction to form an oxide-free region and selective deposition of at least one second metal from said at least one metal source of the second metal selectively at said oxide-free region,
wherein the selective etching and said surface deposition of the second metal are confined to the region at the vicinity of the junction by self-limiting reactions such that the process provides the nanostructure to have growth of the second metal confined to the region at the vicinity of the junction.

2. The process according to claim 1 , wherein first metal of the metal-semiconductor junction is Au and the second metal grown onto or at the vicinity of the junction is Cu, Au or Ag.

3. The process according to claim 1 , wherein the contacting of said nanostructure in solution with the processing solution consists of the immersing of the nanostructure in the processing solution.

4. The process according to claim 1 , wherein the metal of the metal-semiconductor junction is Au and the metal grown onto or at the vicinity of the junction is Au.

5. The process according to claim 1 , wherein the metal of the metal-semiconductor junction is Au and the metal grown onto or at the vicinity of the junction is Ag.

6. The process according to claim 1 , wherein the semiconductor material is a surface region or bulk material of a three-dimensional object.

7. The process according to claim 6 , wherein the three-dimensional object is a feature of an electronic or optoelectronic device.

8. The process according to claim 7 , wherein the object is a semiconductor nanowire.

9. The process according to claim 1 , wherein the nanostructure comprises the metal-semiconductor junction on a substrate comprising the semiconductor and the processing solution contacts the junction and the substrate.

10. A process for forming a metal region at a metal-semiconductor junction of a nanostructure, the nanostructure consisting of a semiconductor material and at least one first metal with an oxide layer on the semiconductor material, wherein a surface of the semiconductor material is decorated with the at least one first metal, wherein the first metal is in direct contact with the surface of the semiconductor material, and wherein a portion of the semi-conductor material with the oxide layer thereon is at a region of the nanostructure at a vicinity of the junction, the process comprising:
contacting the nanostructure in solution with a processing solution comprising:
at least one metal source of a second metal,
at least one reducing agent and
at least one etchant,

wherein said contacting of said nanostructure in solution with the processing solution comprises immersing the nanostructure in the processing solution, said contacting causing selective etching of an oxide layer present on the semiconductor surface of said nanostructure solely at the vicinity of the first metal to form an etched region,
subsequent reduction of the at least one metal source of the second metal to at least one second metal and surface deposition of the at least one second metal at the etched region,
wherein the selective etching and the surface deposition of the second metal are confined to the region at the vicinity of the junction by self-limiting reactions such that the process provides the nanostructure to have growth of the second metal confined to the region at the vicinity of the junction.

11. A process for patterning a nanostructure consisting of a first metal and a semiconductor material with an oxide layer on the semiconductor material, said patterning being at a metal-semiconductor junction of the first metal and the semiconductor material, wherein the first metal is in direct contact with a surface of the semiconductor material, and wherein a portion of the semi-conductor material with the oxide layer thereon is at a region of the nanostructure at a vicinity of the junction,
the process consisting of:
contacting said nanostructure in solution with a processing solution comprising:
at least one etchant,
at least one reducing agent and
at least one metal source of a second metal,
wherein said contacting of said nanostructure in solution with the processing solution is by immersing the nanostructure in the processing solution; said contacting of the nanostructure causing self-processing involving selective etching of the oxide layer at said region solely at a vicinity of the junction to form an oxide-free region and selective deposition of at least one second metal from said at least one metal source of the second metal selectively at said oxide-free region,
wherein the selective etching and said surface deposition of the second metal are confined to the region at the vicinity of the junction by self-limiting reactions.

Assignees

• Yissum Res Dev Co Of Hebrew Univ Jerusalem Ltd

Inventors

• Yerushalmi Roie
• Paltiel Yossef
• Pinchas-Hazut Ori
• Waichman Sharon
• Ziv Amir
• Yochelis Shira

Classifications

• B82Y35/00

  Methods or apparatus for measurement or analysis of nanostructures · CPC title

• B82B1/001

  Devices without movable or flexible elements · CPC title

• B81B2203/0361

  Tips, pillars · CPC title

• B81C1/00031 Primary

  Regular or irregular arrays of nanoscale structures, e.g. etch mask layer (photomechanical, e.g. photolithographic, production of textured or patterned surfaces G03F7/00; lithographic processes for making patterned surfaces using printing and stamping G03F7/0002) · CPC title

• B82Y30/00

  Nanotechnology for materials or surface science, e.g. nanocomposites · CPC title