Method for controlling the tuning to a communications frequency of an antenna connected to a component designed for contactless communication and corresponding system
US-10419058-B2 · Sep 17, 2019 · US
US11075645B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11075645-B2 |
| Application number | US-202016878323-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 19, 2020 |
| Priority date | May 21, 2019 |
| Publication date | Jul 27, 2021 |
| Grant date | Jul 27, 2021 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
An integrated circuit including a first passive component of capacitive, resistive, or inductive type, including: a plurality of second and third passive components of said type, each having a same first theoretical value Compu_t, the second components being connected together so that their values add, and each third component being associated with a first switch having its state determining whether the value of the third component adds to the values of the second components; and a plurality of fourth passive components of said type, each associated with a second switch having its state determining whether the value of the fourth component adds to the values of the second components, at least one of the fourth passive components having a second theoretical value equal to (1−P).Compu_t or to (1+P).Compu_t, P being positive and smaller than ½.
Opening claim text (preview).
The invention claimed is: 1. An integrated circuit comprising a first passive component of capacitive, resistive, or inductive type, comprising: a plurality of second and third passive components of said type, each having a same first theoretical value Comp u _t, the second components being connected together so that their values add, and each third component being associated with a first switch having its state determining whether the value of the third component adds to the values of the second components; and a plurality of fourth passive components of said type, each associated with a second switch having its state determining whether the value of the fourth component adds to the values of the second components, at least one of the fourth passive components having a second theoretical value equal to (1-P) .Comp u _t or to (1+P) .Comp u _t , P being positive and strictly smaller than ½. 2. The circuit according to claim 1 , wherein the first component has a target value equal to M.Compu_t, M being an integer, preferably greater than or equal to 1/P. 3. The circuit according to claim 2 , wherein P.Compu_t determines a maximum desired difference between a practical value and a target value of the first component or a practical value of a fifth passive component the first and fifth components having the same target value and being of the same type. 4. The circuit according to claim 3 , further comprising a measurement circuit configured to deliver a signal representative of a difference between the practical value of the first component and the target value of the first component or the practical value of the fifth component. 5. The circuit according to claim 1 , further comprising a circuit for controlling the first and second switches, configured to select any of the possible combinations of states of the first and second switches. 6. The circuit according to claim 5 , wherein, in a phase of characterization of the first component, the control circuit is configured to successively select at least some of said possible combinations of states of the first and second switches, preferably all of said possible combinations of states of the first and second switches. 7. The circuit according to claim 4 , wherein, in a correction phase, the control circuit is configured to select among the combinations selected during the characterization phase, based on the signal delivered by the measurement circuit for each combination selected during the characterization phase, a combination of states of the first and of second switches corresponding to the practical value of the first component closest to the target value or to the practical value of the fifth component. 8. The circuit according to claim 1 , wherein said components are of capacitive type, the second components being connected in parallel to one another, each third component being series-connected to the first switch having the third component associated therewith, each fourth component being series-connected to the second switch having the fourth component associated therewith, each series association of a third component and of a switch and each series association of a fourth component and of a switch being connected in parallel to the second components. 9. The circuit according to claim 1 , wherein P is smaller than or equal to ⅓, preferably ¼. 10. The circuit according to claim 1 , wherein P is equal to 1/R, R being an integer. 11. The circuit according to claim 10 , comprising M−R second components and R third components. 12. The circuit according to claim 11 , comprising R fourth components. 13. The circuit according to claim 1 , wherein all the fourth components have the same second theoretical value. 14. A digital-to-analog converter comprising the integrated circuit according to claim 1 . 15. An integrated circuit comprising a first passive component of capacitive, resistive, or inductive type, comprising: a plurality of second and third passive components of said type, each having a same first theoretical value Comp u _t, the second components being connected together so that their values add, and each third component being associated with a first switch having its state determining whether the value of the third component adds to the values of the second components; and a plurality of fourth passive components of said type, each associated with a second switch having its state determining whether the value of the fourth component adds to the values of the second components, some of the fourth passive components having a same second theoretical value equal to (1-P).Compu_t or to (1+P).Compu_t, P being positive and strictly smaller than ½, all other fourth passive components having a same third theoretical value equal to (1-P1).Compu_t or to (1+P1).Compu_t, P1 being positive and strictly smaller than ½, P1 being or not equal to P. 16. The circuit according to claim 15 , wherein P is equal to 1/R, R being an integer. 17. The circuit according to claim 16 , comprising M−R second components and R third components. 18. The circuit according to claim 17 , comprising R fourth components. 19. The circuit according to claim 15 , wherein all the fourth components have the same second theoretical value. 20. An integrated circuit comprising a first passive component of capacitive, resistive, or inductive type, comprising: a plurality of second and third passive components of said type, each having a same first theoretical value Comp u t, the second components being connected together so that their values add, and each third component being associated with a first switch having its state determining whether the value of the third component adds to the values of the second components; a plurality of fourth passive components of said type, each associated with a second switch having its state determining whether the value of the fourth component adds to the values of the second components, at least one of the fourth passive components having a second theoretical value equal to ( 1 -P) .Comp u _t or to (1+P) . Comp u _t, P being positive and strictly smaller than ½; wherein the first component has a target value equal to M.Compu_t, M being an integer, preferably greater than or equal to 1/P; wherein P.Compu_t determines a maximum desired difference between a practical value and a target value of the first component or a practical value of a fifth passive component the first and fifth components having the same target value and being of the same type; and further comprising a measurement circuit configured to deliver a signal representative of a difference between the practical value of the first component and the target value of the first component or the practical value of the fifth component; wherein, in a correction phase, the control circuit is configured to select among the combinations selected during the characterization phase, based on the signal delivered by the measurement circuit for each combination selected during the characterization phase, a combination of states of the first and of second switches corresponding to the practical value of the first component closest to the target value or to the practical value of the fifth component.
Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM] · CPC title
Testing passive components (testing relays G01R31/3278; testing electrical windings, e.g. inductors G01R31/72) · CPC title
using digitally programmable trimming circuits · CPC title
with equally weighted capacitors which are switched by unary decoded digital signals · CPC title
using switched capacitors · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.