Analog to digital converter device and method for calibrating clock skew

Patent metadata

Field	Value
Publication number	US-11075640-B1
Application number	US-202017035748-A
Country	US
Kind code	B1
Filing date	Sep 29, 2020
Priority date	May 20, 2020
Publication date	Jul 27, 2021
Grant date	Jul 27, 2021

Abstract

An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit, and a skew adjusting circuit. The ADC circuits are configured to convert an input signal according to interleaved clock signals to generate first quantized outputs. The calibration circuit is configured to perform at least one calibration operation according to the first quantized outputs to generate second quantized outputs. The skew adjusting circuit further includes a first adjusting circuit. The first adjusting circuit is configured to analyze adjacent clock signals according to part of the second quantized outputs to generate adjusting information. The skew adjusting circuit is configured to analyze time difference information within even-numbered sampling periods of the clock signals according to the second quantized outputs and the adjusting information to generate adjustment signals. The adjustment signals are configured to reduce clock skews of the ADC circuits.

First claim

What is claimed is:

1. An analog to digital converter device comprising:
a plurality of analog to digital converter circuits configured to convert an input signal to generate a plurality of first quantized outputs according to a plurality of clock signals;
a calibration circuit configured to perform at least one calibration operation according to the first quantized outputs to generate a plurality of second quantized outputs; and
a skew adjusting circuit further comprising:
a first adjusting circuit configured to analyze adjacent clock signals of the plurality of clock signals according to a part of the plurality of second quantized outputs to generate adjusting information;

wherein the skew adjusting circuit is configured to analyze time difference information within even-numbered sampling periods of the plurality of clock signals according to the plurality of second quantized outputs and the adjusting information to generate a plurality of adjustment signals, wherein the plurality of adjustment signals are configured to reduce at least one clock skew of the plurality of analog to digital converter circuits.

2. The analog to digital converter device of claim 1 , wherein the first adjusting circuit further comprises:
a plurality of computation circuits configured to receive the part of the second quantized outputs, and configured to generate a plurality of first difference signals according to two of the part of the plurality of second quantized outputs, respectively;
a plurality of first absolute value circuits, wherein each of the plurality of first absolute value circuits is configured to perform an first absolute value operation according to a corresponding first difference signal of the plurality of first difference signals, to generate an first absolute value signal correspondingly;
a plurality of first statistical circuits, wherein each of the first statistical circuits is configured to receive the first absolute value signal correspondingly during a predetermined period, and perform a first statistical operation to output a first calculation signal correspondingly;
an first average circuit configured to perform an first average value operation to average the first calculation signals, to generate a first reference signal; and
a first comparison circuit configured to compare each of the first calculation signals with the first reference signal, to generate the adjusting information.

3. The analog to digital converter device of claim 2 , wherein the skew adjusting circuit further comprises:
a second adjusting circuit configured to analyze a plurality of even-numbered quantized outputs of the plurality of second quantized outputs, according to the adjusting information, to generate a first part of the plurality of adjustment signals; and
a third adjusting circuit configured to analyze a plurality of odd-numbered quantized outputs of the plurality of second quantized outputs, to generate a second part of the plurality of adjustment signals.

4. The analog to digital converter device of claim 3 , wherein the second adjusting circuit further comprises:
a delay circuit configured to delay a last one of the plurality of even-numbered quantized outputs to generate a delayed quantized output;
a plurality of first computation circuits configured to receive the delayed quantized output and the plurality of even-numbered quantized outputs in sequence, and the plurality of first computation circuits is configured to generate a plurality of second difference signals according to two signals of the delayed quantized output and the plurality of second quantized outputs respectively;
a plurality of second absolute value circuits, wherein each of the second absolute value circuits is configured to perform a second absolute value operation according to a corresponding second difference signal of the plurality of second difference signals, to generate a second absolute value signal correspondingly;
a plurality of second statistical circuits, wherein each of the plurality of second statistical circuits is configured to receive the second absolute value signal correspondingly during the predetermined period, and is configured to perform a second statistical operation to output a second calculation signal correspondingly;
an second average circuit configured to perform a second average value operation to average the second calculation signals, to generate a second reference signal;
a plurality of second comparison circuits configured to compare the second calculation signals with the second reference signal to generate a plurality of detection signals; and
a plurality of second computation circuits, wherein each of the second computation circuits is configured to perform an addition operation according to the adjusting information and a corresponding detection signal of the plurality of detection signals, to generate the first part of the plurality of adjustment signals.

5. The analog to digital converter device of claim 3 , wherein the third adjusting circuit further comprises:
a delay circuit configured to delay a last one of the plurality of odd-numbered quantized outputs to generate a delayed quantized output;
a plurality of first computation circuits configured to receive the delayed quantized output and the plurality of odd-numbered quantized outputs in sequence, and the plurality of first computation circuits is configured to generate a plurality of second difference signals according to two signals of the delayed quantized output and the plurality of second quantized outputs respectively;
a plurality of second absolute value circuits, wherein each of the second absolute value circuits of the third adjusting circuit is configured to perform a second absolute value operation according to a corresponding second difference signal of the plurality of second difference signals, to generate a second absolute value signal correspondingly;
a plurality of second statistical circuits, wherein each of the plurality of second statistical circuits is configured to receive the second absolute value signal correspondingly during the predetermined period, and is configured to perform a second statistical operation to output a second calculation signal correspondingly;
an second average circuit configured to perform a second average value operation to average the second calculation signals, to generate a second reference signal; and
a plurality of second comparison circuits configured to compare the second calculation signals with the second reference signal to generate a plurality of detection signals, wherein the plurality of detection signals are the second part of the plurality of adjustment signals.

6. A method for calibrating a clock skew comprising:
performing at least one calibration operation according to a plurality of first quantized outputs generated by a plurality of analog to digital converter circuits to generate a plurality of second quantized outputs;
analyzing adjacent clock signals of the plurality of clock signals, according to a part of the plurality of second quantized outputs, by a skew adjusting circuit, to generate adjusting information; and
analyzing time difference information within even-numbered sampling periods of plurality of clock signals according to the plurality of second quantized outputs and the adjusting information, by the skew adjusting circuit, to generate a plurality of adjustment signals;
wherein the adjustment signals are configured to reduce at least one clock skew of the analog to digital converter circuits.

7. The method for calibrating the clock skew of claim 6 , wherein generating the adjusting information comprises:
receiving the part of the plurality of second quantized outputs in sequence, and generating a plurality of fir

Assignees

• Global Unichip Corp
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Kang Wen-Juh
• Chen Yu-Chu
• Han Hsin-Han

Classifications

• H03M1/1033

  over the full range of the converter, e.g. for correcting differential non-linearity · CPC title

• H03M1/1023

  Offset correction (H03M1/1019 takes precedence; removal of offset already present on the analogue input signal H03M1/1295) · CPC title

• H03M1/0836

  of phase error, e.g. jitter · CPC title

• H03M1/04

  using stochastic techniques · CPC title

• H03M1/1215

  using time-division multiplexing · CPC title