Miller clamp driver with feedback bias control

Patent metadata

Field	Value
Publication number	US-11075620-B2
Application number	US-202017071803-A
Country	US
Kind code	B2
Filing date	Oct 15, 2020
Priority date	Aug 2, 2018
Publication date	Jul 27, 2021
Grant date	Jul 27, 2021

Abstract

Aspects provide for a circuit including a voltage supply, a driver, and a feedback bias circuit. The driver includes a first p-type field effect transistor (FET) and a first n-type FET. The voltage supply has an input and an output. The driver has a first input coupled to the voltage supply output, a second input coupled to a first node, and an output coupled to a second node. The first p-type FET has a gate coupled to the output of the driver, a source coupled to the voltage supply output, and a drain coupled to the second node. The first n-type FET has a gate coupled to the output of the second driver, a drain coupled to the second node, and a source coupled to a ground node. The feedback bias circuit has an input coupled to the second node and an output coupled to the voltage supply input.

First claim

What is claimed is:

1. A circuit comprising:
a voltage supply having a supply input and a supply output;
a driver circuit having a first driver input, a second driver input, a first driver output and a second driver output, the first driver input coupled to the supply output, the driver circuit configured to:
receive a first signal at the second driver input;
drive the first driver output with a second signal responsive to the first signal; and
produce a third signal at the second driver output responsive to the first signal;

a feedback circuit having a feedback input and a feedback output, the feedback input coupled to the first driver output and the feedback output coupled to the supply input, wherein the feedback circuit is configured to:
receive a fourth signal at the feedback input; and
produce a fifth signal at the feedback output based on the fourth signal; and

wherein the voltage supply is configured to produce a supply voltage at the supply output responsive to the third signal using level-shifting.

2. The circuit of claim 1 , further comprising a Miller clamp coupled to the first driver output and the second driver output.

3. The circuit of claim 2 , wherein the Miller clamp comprises a low-dropout regulator (LDO).

4. The circuit of claim 1 , wherein the voltage supply produces the supply voltage by modulating a reference signal based on the third signal.

5. The circuit of claim 1 , the driver circuit comprising a pre-driver and a transistor pair, the pre-driver and transistor pair configured to drive the first driver output based on the first signal.

6. The circuit of claim 1 , wherein the driver circuit comprises:
a first transistor having a first control terminal, a first current terminal, and a second current terminal, the first control terminal coupled to the second driver output, the first current terminal coupled to the first driver input, and the second current terminal coupled to the first driver output; and
a second transistor having a second control terminal, a third current terminal, and a fourth current terminal, the third current terminal coupled to the first driver output and the fourth current terminal coupled to a ground terminal.

7. The circuit of claim 1 , wherein the feedback circuit comprises a sense transistor configured to sense the fourth signal.

8. The circuit of claim 1 , wherein the voltage supply comprises:
a current source having a first current source terminal and a second current source terminal;
a first transistor having a first control terminal, a first current terminal, and a second current terminal, the first control terminal coupled to the first current terminal, and the first current terminal coupled to the second current source terminal; and
a second transistor having a second control terminal, a third current terminal, and a fourth current terminal, the second control terminal coupled to the first current source terminal, and the third current terminal coupled to the first current source terminal.

9. A circuit comprising:
a resistor having a first resistor terminal and a second resistor terminal, the second resistor terminal adapted to be coupled to a first transistor;
a first Miller clamp having a first clamp input, a second clamp input, a first clamp output, and a second clamp output, the first clamp output coupled to the first resistor terminal, the second clamp output adapted to be coupled to a second transistor; and
a second Miller clamp having a third clamp input, a fourth clamp output, and a fifth clamp output, the fourth clamp output coupled to the second clamp input, the fifth clamp output adapted to be coupled to the second transistor.

10. The circuit of claim 9 , wherein the first Miller clamp comprises a low drop-out regulator (LDO) and the second Miller clamp comprises an internal voltage supply.

11. The circuit of claim 9 , wherein the first Miller clamp has a first sinking capacity, the second Miller clamp has a second sinking capacity, and the first sinking capacity is greater than the second sinking capacity.

12. The circuit of claim 9 , wherein the second Miller clamp has a sixth clamp output adapted to be coupled to the first transistor.

13. The circuit of claim 9 , wherein the second Miller clamp is configured to control the second transistor to discharge a charge at a gate of the first transistor.

14. The circuit of claim 9 , wherein the second Miller clamp comprises:
a feedback circuit configured to produce a sense current representative of a current at the fifth clamp output; and
an internal voltage supply configured to generate an internal supply voltage responsive to the sense current.

15. The circuit of claim 9 , further comprising the first transistor, wherein the first transistor is a silicon-carbide field effect transistor (SiC FET) or an insulated gate bi-polar transistor (IGBT).

16. The circuit of claim 9 , wherein the first Miller clamp is configured to sink current from a gate of the first transistor in parallel with the second Miller clamp sinking current from the gate of the first transistor.

17. A circuit comprising:
a first resistor having a first resistor terminal and a second resistor terminal;
a second resistor having a third resistor terminal and a fourth resistor terminal, the third resistor terminal coupled to the second resistor terminal;
a first Miller clamp having a first clamp input, a second clamp input, a first clamp output, and a second clamp output, the first clamp output coupled to the first resistor terminal;
a second Miller clamp having a third clamp input, a fourth clamp output, and a fifth clamp output, the fourth clamp output coupled to the second clamp input; and
a comparison circuit having a comparison input, a first comparison output, and a second comparison output, the comparison input coupled to the fourth resistor terminal, the first comparison output coupled to the first clamp input, and the second comparison output coupled to the third clamp input.

18. The circuit of claim 17 , further comprising:
a pull-up circuit coupled between the fourth resistor terminal and a control terminal; and
a pull-down circuit coupled between the second resistor terminal and the control terminal.

19. The circuit of claim 18 , wherein the control terminal is configured to receive a pulse-width modulation (PWM) signal.

20. The circuit of claim 18 , wherein the comparison circuit is configured to control the first Miller clamp and the second Miller clamp based on a comparison of a signal at the comparison input to a threshold.

Assignees

• Texas Instruments Inc

Inventors

• Ju Shuing
• Tan Wenxiao
• Rao Arun

Classifications

• H03K17/0822 Primary

  in field-effect transistor switches · CPC title

• H03K4/48 Primary

  using as active elements semiconductor devices (H03K4/787 - H03K4/84 take precedence) · CPC title