Wide bandgap semiconductor device

Patent metadata

Field	Value
Publication number	US-11075295-B2
Application number	US-201816034536-A
Country	US
Kind code	B2
Filing date	Jul 13, 2018
Priority date	Jul 13, 2018
Publication date	Jul 27, 2021
Grant date	Jul 27, 2021

Abstract

A metal-oxide-semiconductor field-effect transistor includes a wide bandgap substrate, a wide bandgap drift layer over the substrate, a number of junction implants in the drift layer, and a JFET region between the junction implants. The JFET region is defined by a JFET gap, which is the distance between adjacent ones of the junction implants. The JFET gap is not uniform throughout the MOSFET device. The JFET region is separated into a first JFET sub-region and a second JFET sub-region, such that a doping concentration in the first JFET sub-region is different from a doping concentration in the second JFET sub-region.

First claim

What is claimed is:

1. A transistor device comprising:
a wide bandgap substrate;
a wide bandgap drift layer over the wide bandgap substrate;
a plurality of junction implants in the wide bandgap drift layer; and
a junction field-effect transistor (JFET) region between the plurality of junction implants,
wherein:
the JFET region is defined by a JFET gap, which is a distance between adjacent ones of the plurality of junction implants;
the JFET gap is not uniform throughout the transistor device;
the JFET region is separated into a first JFET sub-region and a second JFET sub-region;
a doping concentration of the first JFET sub-region is different from a doping concentration of the second JFET sub-region; and
a transition between the first JFET sub-region and the second JFET sub-region comprises a graded doping concentration that changes in at least one of a linear and step-wise manner in a lateral direction between the doping concentration of the first JFET sub-region and the doping concentration of the second JFET sub-region.

2. The transistor device of claim 1 wherein a JFET gap within the first JFET sub-region is different from a JFET gap within the second JFET sub-region.

3. The transistor device of claim 2 wherein the JFET gap within the first JFET sub-region is smaller than the JFET gap within the second JFET sub-region.

4. The transistor device of claim 3 wherein the doping concentration of the first JFET sub-region is greater than the doping concentration of the second JFET sub-region.

5. The transistor device of claim 1 wherein:
the wide bandgap substrate has a first doping type;
the wide bandgap drift layer has the first doping type; and
the plurality of junction implants each have a second doping type, which is the opposite of the first doping type.

6. The transistor device of claim 1 wherein each one of the plurality of junction implants is rectangular.

7. The transistor device of claim 1 wherein each one of the plurality of junction implants is hexagonal.

8. The transistor device of claim 1 wherein the wide bandgap substrate and the wide bandgap drift layer comprise silicon carbide (SiC).

9. The transistor device of claim 1 wherein the transistor device provides an area normalized on-state resistance less than 2 mΩ-cm 2 and is capable of blocking at least 650 V.

10. The transistor device of claim 1 wherein the doping concentration of the first JFET sub-region is in a range between 1×10 16 cm −3 and 2×10 17 cm −3 and the doping concentration of the second JFET sub-region is in a range between 1×10 15 cm −3 and 5×10 16 cm −3 .

11. A transistor device comprising:
a wide bandgap substrate;
a wide bandgap drift layer over the wide bandgap substrate; and
a plurality of junction implants in the wide bandgap drift layer, the plurality of junction implants arranged in a cell configuration; and
a junction field-effect transistor (JFET) region that comprises a variable doping concentration with a transition that changes in at least one of a linear and step-wise manner in a lateral direction relative to a surface of the wide bandgap drift layer, wherein the transistor device provides an area normalized on-state resistance less than 2 mΩ-cm 2 and is capable of blocking at least 650 V.

12. The transistor device of claim 11 wherein the wide bandgap substrate and the wide bandgap drift layer comprise silicon carbide (SiC).

13. The transistor device of claim 11 wherein a cell (MOS channel) packing density of the transistor device is greater than 370 mm/mm 2 .

14. The transistor device of claim 11 wherein each one of the plurality of junction implants is rectangular.

15. The transistor device of claim 11 wherein each one of the plurality of junction implants is hexagonal.

16. The transistor device of claim 11 wherein the variable doping concentration transitions gradually from a first doping concentration that is in a range between 1×10 16 cm −3 and 2×10 17 cm −3 to a second doping concentration that is in a range between 1×10 15 cm −3 and 5×10 16 cm −3 wherein the second doping concentration is different from the first doping concentration.

17. A method for manufacturing a metal-oxide-semiconductor field-effect transistor (MOSFET) device comprising:
providing a semiconductor stack including a wide bandgap substrate and a wide bandgap drift layer over the wide bandgap substrate;
providing a plurality of junction implants in the wide bandgap drift layer; and
providing a junction field effect transistor (JFET) region between the plurality of junction implants, wherein:
the JFET region is defined by a JFET gap, which is a distance between adjacent ones of the plurality of junction implants;
the JFET gap is not uniform throughout the MOSFET device;
the JFET region is separated into a first JFET sub-region and a second JFET sub-region;
a doping concentration of the first JFET sub-region is different from a doping concentration of the second JFET sub-region; and
a transition between the first JFET sub-region and the second JFET sub-region comprises a graded doping concentration that changes in at least one of a linear and step-wise manner between the doping concentration of the first JFET sub-region and the doping concentration of the second JFET sub-region.

18. The method of claim 17 wherein the graded doping concentration is formed by at least one of a multiple-step masking process, greyscale masking, and pinhole masking.

19. The method of claim 17 wherein the MOSFET device provides an area normalized on-state resistance less than 2 mΩ-cm 2 and is capable of blocking at least 650 V.

20. The method of claim 17 wherein a JFET gap within the first JFET sub-region is different from a JFET gap within the second JFET sub-region.

21. The method of claim 20 wherein the JFET gap within the first JFET sub-region is smaller than the JFET gap within the second JFET sub-region.

22. The method of claim 21 wherein the doping concentration of the first JFET sub-region is greater than the doping concentration of the second JFET sub-region.

Assignees

• Cree Inc

Inventors

• Ryu Sei-Hyung

Classifications

• H10D12/031 Primary

  of IGBTs · CPC title

• H10D62/8325

  Silicon carbide · CPC title

• H10D62/157

  Impurity concentrations or distributions · CPC title

• H10D62/127

  of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs · CPC title

• H10D30/662

  having a drift region having a doping concentration that is higher between adjacent body regions relative to other parts of the drift region · CPC title