Display apparatus

Patent metadata

Field	Value
Publication number	US-11075222-B2
Application number	US-201916511886-A
Country	US
Kind code	B2
Filing date	Jul 15, 2019
Priority date	Dec 17, 2018
Publication date	Jul 27, 2021
Grant date	Jul 27, 2021

Abstract

Provided is a display apparatus. The display apparatus includes an active area and a bezel area, the display apparatus comprising semiconductor patterns disposed in a third area of the bezel area, an insulating layer disposed on the semiconductor patterns and includes contact holes and dummy holes, a power supply electrode disposed in the third area of the bezel area, overlaps the semiconductor patterns with the insulating layer therebetween, and is connected to the semiconductor patterns through the contact holes, dummy gate lines disposed between the semiconductor patterns and the power supply electrode, overlap the semiconductor pattern to form a first compensation capacitance and overlap the power supply electrode to form a second compensation capacitance, and a dummy semiconductor patterns disposed in the third area of the bezel area, and are connected to the power supply electrode through the dummy holes.

First claim

What is claimed is:

1. A display apparatus including an active area, the active area including a first area having a free form portion and a second area which does not have a free form portion, and a bezel area, the bezel area including a third area which is adjacent to the first area and has a free form portion and a fourth area which is adjacent to the second area and does not have a free form portion, the display apparatus comprising:
a plurality of semiconductor patterns disposed in the third area of the bezel area;
an insulating layer disposed on the plurality of semiconductor patterns, the insulating layer made of a plurality of layers;
a power supply electrode disposed in the third area of the bezel area, the power supply electrode overlapping the plurality of semiconductor patterns with the insulating layer therebetween;
a plurality of dummy gate lines disposed between the plurality of semiconductor patterns and the power supply electrode, the plurality of dummy gate lines overlapping the plurality of semiconductor patterns to form a first compensation capacitance and overlapping the power supply electrode to form a second compensation capacitance; and
a plurality of dummy semiconductor patterns disposed in the third area of the bezel area, wherein the plurality of layers includes a gate insulating layer on the plurality of semiconductor patterns and the plurality of dummy semiconductor patterns, a first interlayer insulating layer on the gate insulating layer, and a second interlayer insulating layer on the first interlayer insulating layer,
wherein the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer include a plurality of contact holes which expose the plurality of semiconductor patterns and a plurality of dummy holes which expose the plurality of dummy semiconductor patterns, and
wherein the power supply electrode is connected to the plurality of semiconductor patterns through the plurality of contact holes and is connected to the plurality of dummy semiconductor patterns through the plurality of dummy holes.

2. The display apparatus according to claim 1 , wherein each of the plurality of dummy semiconductor patterns has a smaller area than that of each of the plurality of semiconductor patterns.

3. The display apparatus according to claim 1 , wherein the plurality of dummy semiconductor patterns includes at least one dummy semiconductor pattern disposed in the third area of the bezel area adjacent to a curved portion having a round shape in the first area of the active area.

4. The display apparatus according to claim 1 , wherein the first area of the active area includes a fifth area including a curved portion having a round shape and a notch portion in which one side is removed and a sixth area including only the curved portion, and
the third area of the bezel area includes a seventh area adjacent to the fifth area and an eighth area adjacent to the sixth area.

5. The display apparatus according to claim 4 , wherein the fifth area including the notch portion includes a first sub active area and a second sub active area divided to a left and a right by the notch portion.

6. The display apparatus according to claim 5 , further comprising:
a first gate line and a second gate line disposed in the first sub active area; and
a third gate line and a fourth gate line disposed in the second sub active area.

7. The display apparatus according to claim 6 , wherein the plurality of dummy gate lines include a first dummy gate line and a second dummy gate line, and the first dummy gate line and the second dummy gate line are disposed in the third area of the bezel area disposed between the first sub active area and the second sub active area.

8. The display apparatus according to claim 7 , wherein the first dummy gate line is connected to the first gate line disposed in the first sub active area and the third gate line disposed in the second sub active area, and the second dummy gate line is connected to the second gate line disposed in the first sub active area and the fourth gate line disposed in the second sub active area.

9. The display apparatus according to claim 1 , wherein one of the plurality of semiconductor patterns overlaps at least two contact holes of the plurality of contact holes and the plurality of dummy semiconductor patterns overlaps the plurality of dummy holes.

10. A display apparatus comprising:
a substrate including an active area which includes a notch portion in which one side is removed, and a first sub active area and a second sub active area which display a screen and are divided to a left and a right by the notch portion and a bezel area disposed to be adjacent to the active area;
a plurality of semiconductor patterns of a compensating unit disposed in the bezel area located between the first sub active area and the second sub active area;
a plurality of first dummy semiconductor patterns of a first dummy contact unit disposed between the first sub active area and the compensating unit;
a plurality of second dummy semiconductor patterns of a second dummy contact unit disposed between the second sub active area and the compensating unit;
a power supply line which overlaps the plurality of semiconductor patterns, the plurality of first dummy semiconductor patterns, and the plurality of second dummy semiconductor patterns with an insulating layer therebetween; and
at least one dummy gate line which overlaps the plurality of semiconductor patterns and the power supply line and does not overlap the plurality of first dummy semiconductor patterns and the plurality of second dummy semiconductor patterns.

11. The display apparatus according to claim 10 , wherein the plurality of first dummy semiconductor patterns and the plurality of second dummy semiconductor patterns are disposed adjacent to the notch portion.

12. The display apparatus according to claim 10 , wherein the at least one dummy gate line is disposed in the bezel area located between the first sub active area and the second sub active area.

13. The display apparatus according to claim 10 , wherein each of the plurality of first dummy semiconductor patterns and each of the plurality of second dummy semiconductor patterns have a smaller area than that of each of the plurality of semiconductor patterns.

14. The display apparatus according to claim 10 , wherein the insulating layer includes a plurality of contact holes which expose the plurality of semiconductor patterns, a plurality of first dummy holes which expose the plurality of first dummy semiconductor patterns, and a plurality of second dummy holes which expose the plurality of second dummy semiconductor patterns.

15. The display apparatus according to claim 14 , wherein the power supply line is connected to the plurality of semiconductor patterns through the plurality of contact holes, wherein the power supply line is connected to the plurality of first dummy semiconductor patterns through the plurality of first dummy holes, and wherein the power supply line is connected to the plurality of second dummy semiconductor patterns through the plurality of second dummy holes.

16. The display apparatus according to claim 14 , wherein each of the plurality of semiconductor patterns overlaps at least two of the plurality of contact holes, the plurality of first dummy semiconductor patterns overlap the plurality of first dummy holes with one-to-one correspondence, and the plurality of second dummy semiconductor patterns overlap the plurality of second dummy holes with one-to-one correspondence.

Assignees

• Lg Display Co Ltd

Inventors

• Park Heonkwang
• Park Jongchan
• Um Hyunchul
• Lee Taewon

Classifications

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title

• H10D86/481 Primary

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/411

  characterised by materials, geometry or structure of the substrates · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• H10K59/1213

  the pixel elements being TFTs · CPC title