Semiconductor device including an electrode lower layer and an electrode upper layer and method of manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-11075209-B2
Application number	US-201916385674-A
Country	US
Kind code	B2
Filing date	Apr 16, 2019
Priority date	Sep 26, 2008
Publication date	Jul 27, 2021
Grant date	Jul 27, 2021

Abstract

The semiconductor device according to the present invention includes a ferroelectric film and an electrode stacked on the ferroelectric film. The electrode has a multilayer structure of an electrode lower layer in contact with the ferroelectric film and an electrode upper layer stacked on the electrode lower layer. The electrode upper layer is made of a conductive material having an etching selection ratio with respect to the materials for the ferroelectric film and the electrode lower layer. The upper surface of the electrode upper layer is planarized.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, comprising the steps of:
forming a ferroelectric material film having a surface morphology which is made of a ferroelectric material;
forming a first conductive material film made of a first conductive material on the ferroelectric material film, the first conductive material comprising an IrO 2 film, an Ir film and an IrTa alloy film formed by stacking the IrO 2 film, the Ir film and the IrTa alloy film in this order on the ferroelectric material film;
forming a second conductive material film made of a second conductive material having an etching selection ratio with respect to the ferroelectric material and the first conductive material on the first conductive material film, the second conductive material having Titanium and Nitrogen;
planarizing an upper surface of the second conductive material film by CMP so as to reduce a thickness of the second conductive material to 500 nm, to thereby form a planar surface as the upper surface of the second conductive material film independent of the surface morphology of the ferroelectric material film;
forming an electrode upper layer consisting of the second conductive material film by patterning the second conductive material film after the planarization; and
forming a ferroelectric film consisting of the ferroelectric material film and an electrode lower layer consisting of the first conductive material film by etching the ferroelectric material film and the first conductive material film while using the electrode upper layer as a mask,
forming a hydrogen barrier film covering the ferroelectric film, the electrode lower layer and the electrode upper layer, the hydrogen barrier film having a uniform thickness due to the planar upper surface of the electrode upper layer;
forming an insulating film on the hydrogen barrier film;
forming a via hole penetrating through the insulating film and the hydrogen barrier film from an upper surface of the insulating film to extend into the electrode upper layer in an intermediate portion in the thickness direction of the electrode upper layer;
forming a barrier metal film on an inner surface of the via hole, the barrier metal film having a uniform thickness due to the planar upper surface of the electrode upper layer, and
forming a plug material layer on the barrier metal film to fill the via hole; and
forming a lower electrode to be opposed to the electrode lower layer and the electrode upper layer through the ferroelectric film,
wherein an upper surface of the electrode lower layer includes at least one wave-shaped irregularity,
wherein an interface between the electrode lower layer and the electrode upper layer defines a wave-shaped irregularity having a plurality of peaks in a cross-sectional view,
wherein the via hole has a width which is wider than a distance between adjacent peaks of the wave-shaped irregularity,
wherein a lower surface of the barrier metal film is placed between the highest peak of the plurality of peaks and an upper surface of the electrode upper layer in a vertical direction,
wherein the lower electrode has a same thickness as the thickness of the hydrogen barrier film, and
wherein the thickness of the barrier metal film is smaller than both the thickness of the hydrogen barrier film and that of the lower electrode.

2. The method of manufacturing a semiconductor device according to claim 1 ,
wherein the via hole and the plug material layer are formed such that a lower surface of the hydrogen barrier film is formed at a height between a height of a bottom surface of the via hole and a height of a lower surface of the plug material layer, and
wherein an upper surface of the hydrogen barrier film is located at a height above the height of the lower surface of the plug material layer.

3. The method of manufacturing a semiconductor device according to claim 1 , further comprising the step of:
forming a barrier metal material film on the insulating film including an inner surface of the via hole, wherein
the plug material layer is formed on the barrier metal material film, and
the method further comprises a step of forming the barrier metal film and a plug in the via hole by removing portions of the barrier metal material film and the plug material layer located outside the via hole.

4. The method of manufacturing a semiconductor device according to claim 3 , wherein
the ferroelectric film includes PZT,
the electrode upper layer includes a conductive material having Titanium and Nitrogen,
the upper surface of the electrode upper layer is smoother, relatively, than an upper surface of the ferroelectric film,
an interface between the barrier metal film and the plug is placed under the upper surface of the hydrogen barrier film in a vertical direction, the interface being flat,
the hydrogen barrier film has a generally uniform thickness,
an upper surface of the electrode lower layer has a morphology based on a morphology of the upper surface of the ferroelectric film,
the upper surface of the ferroelectric film and the upper surface of the electrode lower layer have a rough shape based on a morphology of the ferroelectric film,
a thickness of the ferroelectric film is not more than 100 nm,
the hydrogen barrier film includes a composition composed of at least aluminum and oxygen,
a width of the electrode upper layer is smaller than a width of the ferroelectric film, and
a width of the hydrogen barrier film covering surfaces of the ferroelectric film is smaller than the width of the electrode upper layer.

5. The method of manufacturing a semiconductor device according to claim 1 , wherein a lower surface of the electrode upper layer is not planarized.

6. The method of manufacturing a semiconductor device according to claim 1 , wherein the upper surface of the ferroelectric film is smoother, relatively, than an upper surface of the electrode lower layer.

7. The method of manufacturing a semiconductor device according to claim 3 , further comprising the steps of:
forming a transistor electrically connected to a capacitor including at least the ferroelectric film, the electrode lower layer and the electrode upper layer;
forming a second plug electrically connected to the transistor; and
forming a third plug electrically connected to the transistor,
wherein all of the capacitor, the transistor, the second plug and the third plug appear the in one cross-sectional view obtained by linearly cutting the semiconductor device.

8. The method of manufacturing a semiconductor device according to claim 7 , further comprising a step of forming a fourth plug disposed above the third plug in the one sectional view.

9. The method of manufacturing a semiconductor device according to claim 7 , wherein the plug appears on the transistor in the one sectional view.

Assignees

• Rohm Co Ltd

Inventors

• Nakao Yuichi

Classifications

• H10D1/696

  comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688) · CPC title

• H10D1/694

  comprising noble metals or noble metal oxides · CPC title

• H10D1/692

  Electrodes · CPC title

• H10D1/688

  comprising barrier layers to prevent diffusion of hydrogen or oxygen · CPC title

• H10D1/682 Primary

  having dielectrics comprising perovskite structures · CPC title