Semiconductor device and method for fabricating thereof

Patent metadata

Field	Value
Publication number	US-11075160-B2
Application number	US-201916385188-A
Country	US
Kind code	B2
Filing date	Apr 16, 2019
Priority date	Jul 3, 2018
Publication date	Jul 27, 2021
Grant date	Jul 27, 2021

Abstract

A semiconductor device is provided. The semiconductor device includes a first wiring and a second wiring disposed at a first metal level, a third wiring and a fourth wiring disposed at a second metal level different from the first metal level, a first via which directly connects the first wiring and the third wiring, a fifth wiring disposed at a third metal level between the first metal level and the second metal level and connected to the second wiring, and a second via which directly connects the fourth wiring and the fifth wiring.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first wiring and a second wiring at a first metal level;
a third wiring and a fourth wiring at a second metal level different from the first metal level;
a first via which directly connects the first wiring and the third wiring, the first via being integral with the third wiring, the first via being tapered and having a maximum width that is less than a width of the third wiring;
a fifth wiring at a third metal level between the first metal level and the second metal level and connected to the second wiring;
a second via which directly connects the fourth wiring and the fifth wiring;
an etching prevention layer between the first metal level and the second metal level, not on the first wiring and includes an opening, the first via extending through the opening, and
an interlayer insulating layer having portions above the first via,
wherein a width of a bottom portion of the third wiring is greater than a width of a topmost portion of the first via.

2. The semiconductor device of claim 1 , wherein the first via is not in contact with the etching prevention layer.

3. The semiconductor device of claim 1 , further comprising:
an etching prevention layer between the first metal level and the second metal level,
wherein the first via penetrates the etching prevention layer and is in contact with the etching prevention layer.

4. The semiconductor device of claim 1 , further comprising:
a third via which directly connects the second wiring and the fifth wiring.

5. The semiconductor device of claim 4 , further comprising:
a sixth wiring at a fourth metal level between the first metal level and the third metal level; and
an etching prevention layer between the first metal level and the third metal level and including an opening,
wherein the third via passes through the opening.

6. The semiconductor device of claim 5 , wherein the third via is not in contact with the etching prevention layer.

7. The semiconductor device of claim 1 , further comprising:
a sixth wiring in a fourth metal level between the first metal level and the third metal level;
a third via which directly connects the fifth wiring and the sixth wiring; and
a fourth via which directly connects the fifth wiring and the second wiring.

8. The semiconductor device of claim 7 , further comprising:
a first etching prevention layer between the first metal level and the third metal level and including a first opening; and
a second etching prevention layer between the second metal level and the fourth metal level and including a second opening,
wherein the first via passes through the first opening and the second opening.

9. The semiconductor device of claim 8 , wherein the first via is not in contact with the first etching prevention layer and the second etching prevention layer.

10. The semiconductor device of claim 1 , wherein the third wiring and the fourth wiring are directly connected to each other.

11. A semiconductor device comprising:
a first wiring and a second wiring at a first metal level;
a third wiring and a fourth wiring at a second metal level higher than the first metal level;
a first interlayer insulating layer between the first metal level and the second metal level and above the first wiring and second wiring, a second interlayer insulating layer on the first interlayer insulating layer;
a first filling layer which connects the first wiring and the third wiring, and extending through the first interlayer insulating layer and the second interlayer insulating layer, the first filling layer being tapered and having a maximum width that is less than a width of the third wiring, the second interlayer insulating layer having portions above the first via;
a second filling layer in the first interlayer insulating layer and connected to the second wiring; and
a third filling layer in the second interlayer insulating layer and connected to the fourth wiring and the second filling layer, the third filling layer is at the second metal level,
wherein a width of a bottom portion of the third wiring is greater than a width of a topmost portion of the first filling layer.

12. The semiconductor device of claim 11 , wherein the third filling layer is spaced apart from the second filling layer.

13. The semiconductor device of claim 11 , further comprising:
a barrier layer between the second filling layer and the third filling layer,
wherein the barrier layer extends between the third filling layer and the second interlayer insulating layer.

14. The semiconductor device of claim 11 , further comprising:
an etching prevention layer between the first interlayer insulating layer and the second interlayer insulating layer,
wherein the first filling layer penetrates through the etching prevention layer.

15. The semiconductor device of claim 14 , wherein the etching prevention layer includes an opening, and
the first filling layer passes through the opening.

16. The semiconductor device of claim 11 , further comprising:
a fifth wiring at a third metal level between the first metal level and the second metal level,
wherein the fifth wiring including a part of the second filling layer.

17. A semiconductor device comprising:
a first wiring and a second wiring;
a first interlayer insulating layer on the first wiring and the second wiring;
a third wiring in the first interlayer insulating layer;
an etching prevention layer including an opening on the third wiring;
a second interlayer insulating layer on the etching prevention layer;
a fourth wiring and a fifth wiring in the second interlayer insulating layer;
a first trench which exposes a part of the first wiring in the first interlayer insulating layer;
a second trench which exposes a part of the third wiring in the second interlayer insulating layer;
a third trench which penetrates the opening and exposes a part of the second wiring, in the first interlayer insulating layer and the second interlayer insulating layer;
a first via which connects the first wiring and the third wiring in the first trench, the first via being integral with the third wiring, the first via being tapered and having a maximum width that is less than a width of the third wiring, the second interlayer insulating layer having portions above the first via;
a second via which connects the third wiring and the fourth wiring in the second trench; and
a third via which connects the second wiring and the fifth wiring in the third trench,
wherein a width of a bottom portion of the third wiring is greater than a width of a topmost portion of the first via.

18. The semiconductor device of claim 17 , wherein the third via is not in contact with the etching prevention layer.

19. The semiconductor device of claim 17 , wherein the fourth wiring and the fifth wiring are directly connected to each other.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Doo-Hwan
• Park Seong Ho
• Park Kyoung Pil
• Bae Tae Yong
• Seo Eun-Chul

Classifications

• H10W20/421

  Skip vias, i.e. vias that do not connect all metallization layers that they pass through · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/074

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title

• H10W20/056 Primary

  by filling conductive material into holes, grooves or trenches · CPC title