Spice circuit model for twinaxial cable
US-9542516-B1 · Jan 10, 2017 · US
Method for simulating signal integrity of hybrid model
US11074384B1 · US · B1
| Field | Value |
|---|---|
| Publication number | US-11074384-B1 |
| Application number | US-201716097217-A |
| Country | US |
| Kind code | B1 |
| Filing date | Dec 28, 2017 |
| Priority date | Aug 10, 2017 |
| Publication date | Jul 27, 2021 |
| Grant date | Jul 27, 2021 |
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Abstract
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A method for simulating signal integrity of a hybrid model is provided, which includes: establishing a transient simulation link including a front-end chip model, a pre-link model and a terminating impedance model, where the front-end chip model is a Spice model; inputting an ideal step signal to a port reserved in the front-end chip model, and extracting step response data in a steady state; inputting the step response data to an input end of a channel simulation link, where the channel simulation link includes a relay chip model, a post-link model and a back-end chip model, and each of the relay chip model and the back-end chip model is an IBIS AMI model; and inputting a random code signal to the input end of the channel simulation link, and reading a signal outputted from an output end of the back-end chip and forming an eye pattern.
First claim
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The invention claimed is: 1. A method for simulating signal integrity of a hybrid model, comprising: establishing a transient simulation link, wherein the transient simulation link comprises a front-end chip model, a pre-link model arranged at an output end of the front-end chip model and a terminating impedance model arranged at a tail end of the pre-link model, and the front-end chip model is a Spice model; inputting an ideal step signal to a port reserved in the front-end chip model, and extracting step response data in a steady state outputted from the tail end of the pre-link model; inputting the step response data to an input end of a channel simulation link, wherein the channel simulation link comprises a relay chip model, a back-end chip model and a post-link model for connecting the relay chip model and the back-end chip model, and each of the relay chip model and the back-end chip model is an IBIS AMI model; and inputting a random code signal to the input end of the channel simulation link, and reading a signal outputted from an output end of the back-end chip model and forming an eye pattern. 2. The method according to claim 1 , wherein the pre-link model and/or the post-link model is a model using S-parameters. 3. The method according to claim 2 , wherein the pre-link model and/or the post-link model is a wiring model having a length of 5 inches. 4. The method according to claim 1 , further comprising: reading a signal outputted from an output end of the post-link model and forming an eye pattern. 5. The method according to claim 2 , further comprising: reading a signal outputted from an output end of the post-link model and forming an eye pattern. 6. The method according to claim 3 , further comprising: reading a signal outputted from an output end of the post-link model and forming an eye pattern.
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Classifications
- G06F30/367Primary
Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title
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- What does patent US11074384B1 cover?
- A method for simulating signal integrity of a hybrid model is provided, which includes: establishing a transient simulation link including a front-end chip model, a pre-link model and a terminating impedance model, where the front-end chip model is a Spice model; inputting an ideal step signal to a port reserved in the front-end chip model, and extracting step response data in a steady state; i…
- Who is the assignee on this patent?
- Zhengzhou Yunhai Information Tech Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification G06F30/367. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Jul 27 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).