Access to dynamic address translation across multiple spaces for operational context subspaces

Patent metadata

Field	Value
Publication number	US-11074195-B2
Application number	US-201916456006-A
Country	US
Kind code	B2
Filing date	Jun 28, 2019
Priority date	Jun 28, 2019
Publication date	Jul 27, 2021
Grant date	Jul 27, 2021

Abstract

A computer-implemented method for switching between a full space and a subspace across multiple address spaces is described. A non-limiting example of the computer-implemented method includes determining, by a processor, that switching between the full space and the subspace is enabled by examining a bit in a control register. The method determines, by the processor, that there is a new context different from an existing context based on the bit in the control register indicating that switching is enabled and switches, by the processor, the context of the multiple spaces based on determining that the new context is different from the existing context.

First claim

What is claimed is:

1. A computer-implemented method of switching spaces having contexts between a full space context in memory storage and a subspace context of memory storage comprising:
determining, by a processor, that switching between the full space and the subspace is enabled by examining a bit in a control register;
determining, by the processor, that there is a new context different from an existing context based on the bit in the control register indicating that switching is enabled; and
switching, by the processor, the context of the spaces based on determining that the new context is different from the existing context.

2. The computer-implemented method of claim 1 , further comprising:
determining, by the processor, that the subspace will be used by the new context; and
creating, by the processor, the full space for all contexts and invalidating entries in the full space for alternate contexts.

3. The computer-implemented method of claim 2 , further comprising creating, by the processor, the subspace.

4. The computer-implemented method of claim 1 , further comprising:
determining, by the processor, that the subspace will be used; and
creating, by the processor, only the full space.

5. The computer-implemented method of claim 4 , further comprising creating, by the processor, the subspace.

6. The computer implemented method of claim 1 , further comprising determining, by the processor, that a faulting instruction was using the susbspace when a fault occurs.

7. The computer-implemented method of claim 6 , further comprising performing fault processing normally, by the processor, based on the faulting instruction not using the subspace.

8. The computer-implemented method of claim 1 , wherein each space comprises an address space second table entry (ASTEs), dispatchable unit control tables (DUCTs), access lists, and destination ASTEs (DASTEs).

9. A system for switching spaces having contexts between a full space context and a subspace context comprising:
a processor;
a memory communicatively coupled to the processor, the memory having stored therein instructions that when executed cause the processor to:
determine that switching between the full space and the subspace is enabled by examining a bit in a control register;
determine that there is a new context different from an existing context based on the bit in the control register indicating that switching is enabled; and
switch the context of the spaces based on determining that the new context is different from the existing context.

10. The system of claim 9 , further comprising instructions that cause the processor to:
determine that the subspace will be used by the new context; and
create the full space for all contexts and invalidating entries in the full space for alternate contexts.

11. The system of claim 10 , further comprising instructions that cause the processor to create the subspace.

12. The system of claim 9 , further comprising instructions that cause the processor to:
determine that the subspace will be used; and
create only the full space.

13. The system of claim 12 , further comprising instructions that cause the processor to create the subspace.

14. The system of claim 9 , further comprising instructions that cause the processor to determine that a faulter was using the susbspace when a fault occurs.

15. The system of claim 14 , further comprising instructions that cause the processor to perform fault processing normally based on the faulter not using the subspace.

16. The system of claim 9 , wherein each space comprises an address space second table entry (“ASTEs”), dispatchable unit control tables (“DUCTs”), access lists, and destination ASTE's (“DASTEs”).

17. A computer program product for switching spaces having contexts between a full space context and a subspace context, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to:
determine that switching between the full space and the subspace is enabled by examining a bit in a control register;
determine that there is a new context different from an existing context based on the bit in the control register indicating that switching is enabled; and
switch the context of the spaces based on determining that the new context is different from the existing context.

18. The computer program product of claim 17 , further comprising instructions that cause the processor to:
determine that the subspace will be used by the new context; and
create the full space for all contexts and invalidating entries in the full space for alternate contexts.

19. The computer program product of claim 18 , further comprising instructions that cause the processor to create the subspace.

20. The computer program product of claim 17 , further comprising instructions that cause the processor to:
determine that the subspace will be used; and
create only the full space.

Assignees

• IBM

Inventors

• Tzortzatos Elpida
• Partlow Steven M
• Compton Scott B
• Yost Christine Michele
• Relson Peter Jeremy

Classifications

• G06F12/1009

  using page tables, e.g. page table structures · CPC title

• G06F12/08

  in hierarchically structured memory systems, e.g. virtual memory systems · CPC title

• G06F12/109 Primary

  for multiple virtual address spaces, e.g. segmentation (G06F12/1036 takes precedence) · CPC title

• G06F2212/651

  Multi-level translation tables · CPC title

• G06F2212/1016

  Performance improvement · CPC title