Multi-core audio processor with low-latency sample processing core

Patent metadata

Field	Value
Publication number	US-11074032-B2
Application number	US-201816649945-A
Country	US
Kind code	B2
Filing date	Sep 24, 2018
Priority date	Sep 29, 2017
Publication date	Jul 27, 2021
Grant date	Jul 27, 2021

Abstract

A multi-core audio processor includes a data protocol interface configured to receive a stream of audio data, a plurality of data processing cores including a single sample processing core and a block data processing core, an audio fabric block configured to route samples of the stream between the data protocol interface and the plurality of data processing cores. The single sample processing core includes an execution unit configured to execute one or more low latency instructions for performing computations for the samples.

First claim

What is claimed is:

1. A multi-core audio processor comprising:
a data protocol interface configured to receive a stream of audio data;
a plurality of data processing cores including a single sample processing core and a block data processing core; and
an audio fabric block configured to route samples of the stream between the data protocol interface and the plurality of data processing cores,
wherein the single sample processing core comprises an execution unit configured to execute one or more low latency instructions for performing computations for the samples.

2. The multi-core audio processor of claim 1 , wherein the execution unit is a first vector execution unit comprising a cosine operation unit, a sine operation unit and an exponential operation unit, the first vector execution unit configured to compute first, second and third outputs in a single execution cycle of the first low latency instruction.

3. The multi-core audio processor of claim 1 , wherein the single sample processing core comprises:
an instruction memory interface communicably coupled to a memory, the memory storing a first low latency instruction, the first low latency instruction taking at least two inputs;
a data memory interface communicably coupled to the audio fabric block; and
a first vector register file communicably coupled to the data memory interface, the vector register file including a first vector register storing the at least two inputs, wherein the execution unit includes a first vector execution unit communicably coupled to the first vector register file, wherein the first vector execution unit is configured to perform multiple operations on one of the at least two inputs in a single execution of the low latency instruction and store the results in a second vector register of the vector register file.

4. The multi-core audio processor of claim 2 , wherein the single sample processing core further comprises a second vector execution unit, the second vector execution unit including a multiplication operation unit configured to multiply the third output by a combination of the first and second outputs of the first vector execution unit to generate a filter coefficient.

5. The multi-core audio processor of claim 1 , wherein the single sample processing core further comprises an additional execution unit configured to generate a filtered sample based on input sampling rate coefficients applied to an input sample received from the audio fabric block and to store the filtered sample in a data buffer.

6. The multi-core audio processor of claim 5 , wherein the additional execution unit is configured to apply output sampling rate coefficients to generate a set of scaled samples used to generate output samples at a different sampling rate than a sampling rate of the stream.

7. The multi-core audio processor of claim 1 , wherein the single sample processing core further comprises:
a vector register file; and
a vector execution unit communicably coupled to the vector register file, the vector execution unit having a plurality of hard-wired routes coupling the vector register file to multiplication units of the vector execution unit.

8. The multi-core audio processor of claim 7 , further comprising a set of state registers communicably coupled to the vector execution unit, the state registers storing a plurality of assignment vectors assigning vector locations in the vector register file to the multiplication units, the vector execution unit configurable to selectively retrieve an assignment vector from the set of state registers based on a field input.

9. A multi-core audio processor comprising:
a data protocol interface configured to receive a stream of audio data, the stream of audio data having a first sampling rate;
a plurality of data processing cores including a single sample processing core and a block data processing core;
an audio fabric block configured to route samples of the stream between the data protocol interface and the plurality of data processing cores;
wherein the single sample processing core comprises a first execution unit configured to execute a first instruction for computing multiple values used to filter a sample in a single instruction cycle, the first instruction comprising one or both of a complex exponential instruction and a sample rate conversion instruction.

10. The multi-core audio processor of claim 9 , wherein the single sample processing core comprises:
a register file communicably coupled to the first execution unit, the register file configured to store an angle and a magnitude of a pole coefficient of a phasor filter, wherein the first instruction configures the first execution unit to compute a sine of the angle, a cosine of the angle, and an exponential function of the magnitude.

11. The multi-core audio processor of claim 10 , wherein the register file is a vector register file storing the angle and the magnitude in a single vector register thereof.

12. The multi-core audio processor of claim 9 , wherein the single sample processing core further comprises a second execution unit configured to execute a second instruction that computes a quotient based on an elapsed time in units of input samples and an output sample time increment.

13. The multi-core audio processor of claim 12 , wherein the audio fabric block further includes an input sample counter communicably coupled to the single sample processing core, the input sample counter configured to count a number of samples of the physical stream received at the data protocol interface, wherein the single sample processing core is configured to compute the elapsed time based on the number of samples of the physical stream and a presentation time of the input sample.

14. The multi-core audio processor of claim 12 , wherein the single sample processing core is configured to execute an output stage of a phasor filter a number of times that corresponds to the quotient.

15. The multi-core audio processor of claim 12 , wherein the second execution unit executes a Sweeney, Robertson, and Tocher (SRT) division algorithm to generate a six bit quotient.

16. The multi-core audio processor of claim 9 , wherein the single sample processing core further comprises a filter coefficient execution unit configured by an instruction to generate filter coefficients based on outputs received from the first execution unit.

17. A single sample audio processing core comprising:
an instruction memory interface communicably coupled to a memory;
a data memory interface configured to receive a sample of audio input data;
a vector register file communicably coupled to the data memory interface;
an execution unit communicably coupled to the vector register file, the execution unit including a plurality of operation units and hard-wired routes from inputs of the operation units to locations of the vector register file; and
a set of state registers communicably coupled to the execution unit, the set of state registers configured to store assignment vectors assigning locations of the vector register file to the inputs of the operation units, wherein the execution unit is configured to execute an instruction having two vector inputs and an immediate field, the immediate field identifying locations of the vector register file or one of the assignment vectors.

18. The single sample audio processing core of claim 17 , wherein the execution unit includes a logic unit configured to enable at least one of the hard-wired routes based on a bit value of the immediate field.

19. The single sample a

Assignees

• Knowles Electronics Llc

Inventors

• Rub Leonardo
• Clark Brian

Classifications

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F3/162 Primary

  Interface to dedicated audio devices, e.g. audio drivers, interface to CODECs · CPC title

• G06F15/7817

  Specially adapted for signal processing, e.g. Harvard architectures · CPC title

• G06F15/76 Primary

  Architectures of general purpose stored program computers (with program plugboard G06F15/08; multicomputers G06F15/16) · CPC title

• G06F15/8053

  Vector processors · CPC title