Methods and apparatus for transistor health monitoring

Patent metadata

Field	Value
Publication number	US-11070197-B1
Application number	US-201916731474-A
Country	US
Kind code	B1
Filing date	Dec 31, 2019
Priority date	Dec 31, 2019
Publication date	Jul 20, 2021
Grant date	Jul 20, 2021

Abstract

Methods, apparatus, systems and articles of manufacture are described for transistor health monitoring. An example gate driver includes a request receiver pin, a measurement transmitter pin, and a driver control logic pin, the request receiver pin, the measurement transmitter pin, and the driver control logic pin configured to be coupled to a controller, a sensing pin, the sensing pin to be coupled to a sensing circuit, a control logic circuit having an input coupled to the request receiver pin, a transistor coupled to the control logic circuit and the sensing pin, a multiplexer coupled to the control logic circuit and the sensing pin, an analog-to-digital converter (ADC) coupled to the multiplexer and the measurement transmitter pin, and a driver control logic circuit coupled to the driver control logic pin.

First claim

What is claimed is:

1. A gate driver comprising:
a request receiver pin configured to be coupled to a controller;
a measurement transmitter pin configured to be coupled to the controller;
a driver control logic pin configured to be coupled to the controller;
a sensing pin configured to be coupled to a sensing circuit;
a control logic circuit having an input coupled to the request receiver pin;
a transistor coupled to the control logic circuit and the sensing pin;
a multiplexer having a first input coupled to the control logic circuit and a second input coupled to the sensing pin;
an analog-to-digital converter (ADC) coupled to the multiplexer and the measurement transmitter pin; and
a driver control logic circuit coupled to the driver control logic pin.

2. The gate driver of claim 1 , wherein the ADC has an input and an output, the input is coupled to the multiplexer, the output is coupled to the measurement transmitter pin, and the ADC to be coupled to the controller via the measurement transmitter pin.

3. The gate driver of claim 1 , further including a voltage input pin, and wherein the multiplexer has a first input, a second input, and an output, the first input is coupled to the control logic circuit, the second input is coupled to the sensing pin and the voltage input pin, and the multiplexer to be coupled to the sensing circuit via the sensing pin.

4. The gate driver of claim 3 , wherein the transistor is a first transistor, and the sensing circuit includes:
a first diode having a first anode and a first cathode, the first cathode to be coupled to the sensing pin;
a second diode having a second anode and a second cathode, the second cathode to be coupled to a second transistor;
a capacitor having a first capacitor terminal and a second capacitor terminal, the first capacitor terminal coupled to the first cathode, the first capacitor terminal to be coupled to the sensing pin, the second capacitor terminal coupled to the first anode; and
a resistor having a first resistor terminal and a second resistor terminal, the first resistor terminal coupled to the first cathode and the first capacitor terminal, the first resistor terminal to be coupled to the sensing pin, the second resistor terminal coupled to the second anode.

5. The gate driver of claim 1 , further including a voltage input pin and a comparator having a first input, a second input, and an output, the first input coupled to the voltage input pin and the transistor, the second input coupled to a reference voltage input, and the output coupled to the control logic circuit.

6. The gate driver of claim 1 , further including a voltage input pin, a sensing pin, and a comparator, and wherein the transistor is a N-channel metal-oxide-semiconductor field-effect transistor (MOSFET) having a gate and a current terminal, the gate coupled to the control logic circuit, the current terminal coupled to the voltage input pin, the sensing pin, and an input of the comparator.

7. The gate driver of claim 1 , wherein the transistor is a first transistor, and further including a first pin, a second pin, and a third pin, the first through third pins coupled to the driver control logic circuit, the first through third pins to be coupled to a second transistor.

8. A gate driver comprising:
a pin adapted to be coupled to a controller;
a first transistor;
a multiplexer;
a control logic circuit having a first output coupled to an input of the multiplexer and a second output coupled to the first transistor, the control logic circuit configured to turn off the first transistor to bias a first diode of a desaturation circuit configured to be coupled to the multiplexer, the desaturation circuit to measure a first voltage associated with a second transistor in response to the biasing of the first diode; and
an analog-to-digital converter (ADC) coupled to the multiplexer, the ADC to convert the first voltage to a digital output, the digital output to be obtained by the controller via the pin.

9. The gate driver of claim 8 , wherein the control logic circuit measures the first voltage in response to a first request from a controller, and further including:
a driver control logic circuit to be coupled to the second transistor, the first request to be generated in response to the driver control logic circuit turning on the second transistor; and
the control logic circuit configured to:
in response to obtaining a second request from the controller, turn off the first transistor to cause the desaturation circuit to generate a second voltage associated with the second transistor, the second request to be generated in response to the driver control logic circuit turning off the second transistor and a negative current flowing through a body diode of the second transistor; and
instruct the multiplexer to send the second voltage to the ADC, the ADC to send the second voltage to the controller via the pin.

10. The gate driver of claim 8 , wherein the control logic circuit measures the first voltage in response to a first request from a controller, and further including:
a driver control logic circuit to be coupled to the second transistor, the first request to be generated in response to the driver control logic circuit turning on the second transistor; and
the control logic circuit configured to:
in response to obtaining a second request from the controller, turn off the first transistor to cause the desaturation circuit to generate a second voltage associated with the second transistor, the second request to be generated in response to the driver control logic circuit turning on the second transistor and a negative current flowing through a body diode of the second transistor; and
instruct the multiplexer to send the second voltage to the ADC, the ADC to send the second voltage to the controller via the pin.

11. The gate driver of claim 8 , wherein the second transistor is a silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET), and further including a driver control logic circuit configured to control the SiC MOSFET.

12. A system comprising:
a controller;
a desaturation circuit including a diode;
a transistor coupled to the desaturation circuit; and
a gate driver coupled to the controller, the desaturation circuit, and the transistor, the gate driver configured to:
in response to a request from the controller, bias the diode to generate a first voltage associated with the transistor; and
transmit the first voltage to the controller; and

the controller configured to generate an alert indicative of a health parameter associated with the transistor based on a comparison of the first voltage to a second voltage, the second voltage generated by the desaturation circuit prior to the first voltage.

13. The system of claim 12 , wherein the transistor is a first transistor, and the gate driver includes:
a second transistor;
a multiplexer;
a control logic circuit coupled to the multiplexer and the second transistor;
an analog-to-digital converter (ADC) coupled to the multiplexer; and
a driver control logic circuit coupled to the first transistor.

14. The system of claim 13 , wherein the control logic circuit is configured to:
obtain the request from the controller;
in response to obtaining the request from the controller, turn off the second transistor to bias the diode; and
instruct the multiplexer to transmit the first voltage to the ADC, the ADC is to transmit the first voltage to the controller.

15. The system of claim 12 , wherein the desaturation circuit includes a resistor coupled to the diode, the controller

Assignees

• Texas Instruments Inc

Inventors

• Wang Gangyao
• Mukhopadhyay Rajarshi
• Aguirre Miguel

Classifications

• H03K17/08 Primary

  Modifications for protecting switching circuit against overcurrent or overvoltage · CPC title

• G01R31/2621

  for testing field effect transistors, i.e. FET's · CPC title

• H03K17/18 Primary

  Modifications for indicating state of switch · CPC title

• H03K17/145

  in field-effect transistor switches · CPC title

• H03K17/687

  the devices being field-effect transistors · CPC title