Oscillator circuit arrangement

Patent metadata

Field	Value
Publication number	US-11070170-B2
Application number	US-201816771616-A
Country	US
Kind code	B2
Filing date	Dec 5, 2018
Priority date	Dec 13, 2017
Publication date	Jul 20, 2021
Grant date	Jul 20, 2021

Abstract

An oscillator circuit arrangement comprises an inverter having input and output terminals that are to be connected to a crystal device. An automatic gain control device controls a current source that supplies current to the inverter. First and second diode devices having different orientation are connected between the input and the output of the inverter. The oscillator consumes low power and has a fast recovery time after an electromagnetic interference event. The oscillator can be used in electronic labels.

First claim

The invention claimed is:

1. An oscillator circuit arrangement, comprising:
an inverter having an input terminal and an output terminal to be connected to a crystal device and having a supply terminal;
an automatic gain control device connected to the output terminal of the inverter and connected to a controllable current source that is connected to the supply terminal of the inverter; and
a first diode device and a second diode device having different orientation and connected between the input and the output of the inverter,
wherein the first diode device has a gate terminal and a drain terminal that are connected with each other and are connected to the input of the inverter and has a source terminal that is connected to the output of the inverter.

2. The oscillator circuit arrangement according to claim 1 , further comprising a controllable resistor connected between the input and output terminals of the inverter and a current path comprising another controllable current source controlled by the output of the automatic gain control device, the current path controlling the controllable resistor.

3. The oscillator circuit arrangement according to claim 2 , wherein the current path includes at least one resistive element (MN 3 , MN 2 ) through which the controllable current source (MP 3 ) of the current path is connected to a terminal for a ground potential (GND).

4. The oscillator circuit arrangement according to claim 3 , wherein the at least one resistive element of the current path comprises a series connection of a first and a second diode device.

5. The oscillator circuit arrangement according to claim 4 , further comprising a third diode device connected between one of the first and second diode devices of the resistive element of the current path and the output terminal of the inverter.

6. The oscillator circuit arrangement according to claim 5 ,
wherein the third diode device comprises a MOS transistor of which the gate and drain terminals are connected with each other.

7. The oscillator circuit arrangement according to claim 2 , wherein the first and second diode devices each comprise a MOS transistor of which the gate and drain terminals are connected with each other.

8. The oscillator circuit arrangement according to claim 4 , wherein the first and second diode devices of the resistive element each comprise a MOS transistor of which the gate and drain terminals are connected with each other.

9. The oscillator circuit arrangement according to claim 6 , wherein the MOS transistors of the first, second and third diode devices and the controllable resistor, in each case, are n-channel-MOS transistor.

10. The oscillator circuit arrangement according to claim 3 , wherein the controllable current sources, in each case, are a p-channel-MOS transistor whose gate terminal is connected to the output of the automatic gain control device.

11. The oscillator circuit arrangement according to claim 1 , wherein the second diode device has a gate terminal and a drain terminal that are connected with each other and are connected to the output of the inverter and has a source terminal that is connected to the input of the inverter.

12. The oscillator circuit arrangement according to claim 1 , wherein the automatic gain control device generates an output signal that has a high gain close to the startup operational phase of the oscillator and has a low gain in the steady state operational phase of the oscillator.

13. The oscillator circuit arrangement according to claim 1 ,
wherein the oscillator circuit comprises a terminal for a supply potential,
wherein the controllable current source is connected to the terminal for a supply potential and the supply terminal of the inverter, the controllable current source having a control terminal,
wherein the automatic gain control device has an input terminal, connected to the output terminal of the inverter and an output terminal connected to the control terminal of the controllable current source,
wherein the first and second diode devices each comprise a MOS transistor having gate, drain and source terminals of which gate and drain terminals are connected with each other.

14. An electronic label device comprising a display device and the oscillator circuit arrangement comprising:
an inverter having an input terminal and an output terminal to be connected to a crystal device and having a supply terminal;
an automatic gain control device connected to the output terminal of the inverter and connected to a controllable current source that is connected to the supply terminal of the inverter; and
a first diode device and a second diode device having different orientation and connected between the input and the output of the inverter, wherein the first diode device has a gate terminal and a drain terminal that are connected with each other and are connected to the input of the inverter and has a source terminal that is connected to the output of the inverter,
wherein the oscillator circuit arrangement provides a clock signal to control display of information on the display device.

15. An oscillator circuit arrangement, comprising:
an inverter having an input terminal and an output terminal to be connected to a crystal device and having a supply terminal;
an automatic gain control device connected to the output terminal of the inverter and connected to a controllable current source that is connected to the supply terminal of the inverter; and
first and second diode devices having different orientation and connected between the input and the output of the inverter,
wherein the second diode device has a gate terminal and a drain terminal that are connected with each other and are connected to the output of the inverter and has a source terminal that is connected to the input of the inverter.

16. The oscillator circuit arrangement according to claim 15 , further comprising a controllable resistor connected between the input and output terminals of the inverter and a current path comprising another controllable current source controlled by the output of the automatic gain control device, the current path controlling the controllable resistor.

17. The oscillator circuit arrangement according to claim 16 , wherein the current path includes at least one resistive element (MN 3 , MN 2 ) through which the controllable current source (MP 3 ) of the current path is connected to a terminal for a ground potential (GND).

18. The oscillator circuit arrangement according to claim 17 , wherein the at least one resistive element of the current path comprises a series connection of a first and a second diode device.

19. The oscillator circuit arrangement according to claim 18 , further comprising a third diode device connected between one of the first and second diode devices of the resistive element of the current path and the output terminal of the inverter.

20. The oscillator circuit arrangement according to claim 19 ,
wherein the third diode device comprises a MOS transistor of which the gate and drain terminals are connected with each other.

21. The oscillator circuit arrangement according to claim 16 , wherein the first and second diode devices each comprise a MOS transistor of which the gate and drain terminals are connected with each other.

22. The oscillator circuit arrangement according to claim 19 , wherein the first and second diode devices of the resistive element each comprise a MOS transistor of which the gate and drain terminals are connec

Assignees

• Ams Ag

Inventors

• Akbari-Dilmaghani Rahim

Classifications

• H03K3/013 Primary

  Modifications of generator to prevent operation by noise or interference · CPC title

• H03B2200/0012

  Pierce oscillator · CPC title

• H03K3/014

  Modifications of generator to ensure starting of oscillations · CPC title

• H03K3/3545

  Stabilisation of output, e.g. using crystal · CPC title

• H03B5/364 Primary

  the amplifier comprising field effect transistors (H03B5/366 takes precedence) · CPC title