Transistor having vertical structure and electric device

Patent metadata

Field	Value
Publication number	US-11069814-B2
Application number	US-201916575077-A
Country	US
Kind code	B2
Filing date	Sep 18, 2019
Priority date	Nov 16, 2018
Publication date	Jul 20, 2021
Grant date	Jul 20, 2021

Abstract

An electronic device can include a panel; a driver circuit configured to drive the panel; and a transistor disposed in the panel, the transistor including: a gate electrode disposed on a substrate, a first insulating film disposed on the gate electrode, an active layer disposed on the first insulating film, the active layer including: a first portion of the active layer overlapping with an upper surface of the gate electrode, a second portion of the active layer extending from the first portion, being disposed along a side surface of the gate electrode and including a channel area, and a third portion of the active layer extending from the second portion of the active layer, the third portion of the active layer being disposed on a portion of the first insulating film that does not overlap with the gate electrode, a second insulating film disposed on the active layer, a first electrode disposed on the second insulating film, the first electrode being electrically connected to the first portion of the active layer, and a second electrode disposed on the second insulating film, the second electrode being electrically connected to the third portion of the active layer.

First claim

What is claimed is:

1. An electronic device comprising:
a panel;
a driver circuit configured to drive the panel; and
a transistor disposed in the panel, the transistor including:
a gate electrode disposed on a substrate,
a first insulating film disposed on the gate electrode,
an active layer disposed on the first insulating film, the active layer including:
a first portion of the active layer overlapping with an upper surface of the gate electrode,
a second portion of the active layer extending from the first portion, being disposed along a side surface of the gate electrode and including a channel area, and
a third portion of the active layer extending from the second portion of the active layer, the third portion of the active layer being disposed on a portion of the first insulating film that does not overlap with the gate electrode,

a second insulating film disposed on the active layer,
a first electrode disposed on the second insulating film, the first electrode being electrically connected to the first portion of the active layer,
a second electrode disposed on the second insulating film, the second electrode being electrically connected to the third portion of the active layer, and
an insulation pattern disposed between the active layer and the second insulating film, in an area corresponding to the side surface of the gate electrode.

2. The electronic device according to claim 1 , wherein the side surface of the gate electrode has a reverse tapered shape or the gate electrode has a stepped portion located in an area corresponding to the second portion of the active layer.

3. The electronic device according to claim 2 , wherein the gate electrode has a single-layer structure, and
wherein a width of the gate electrode increases in a direction away from the substrate.

4. The electronic device according to claim 1 , wherein the insulation pattern overlaps the channel area of the active laver.

5. The electronic device according to claim 1 , wherein a width of the insulation pattern is wider than a width of the channel area of the active layer.

6. The electronic device according to claim 1 , wherein the gate electrode has a multi-layer structure.

7. The electronic device according to claim 6 , wherein the gate electrode includes a first gate electrode and a second gate electrode disposed on the first gate electrode, and
wherein a width of the first gate electrode is narrower than a width of the second gate electrode.

8. The electronic device according to claim 7 , wherein a material of the first gate electrode differs from a material of the second gate electrode.

9. The electronic device according to claim 7 , wherein the channel area of the active layer is disposed to correspond to a portion of a side surface of the first gate electrode.

10. The electronic device according to claim 7 , wherein the gate electrode further includes a third gate electrode disposed under the first gate electrode, and
wherein the width of the first gate electrode is narrower than a width of the third gate electrode.

11. The electronic device according to claim 10 , wherein a material of the first gate electrode differs from both a material of the second gate electrode and a material of the third gate electrode.

12. The electronic device according to claim 1 , wherein one of the first electrode and the second electrode overlaps with an upper surface of the gate electrode.

13. The electronic device according to claim 1 , wherein the first electrode and the second electrode do not overlap with each other.

14. The electronic device according to claim 1 , wherein the first insulating film is denser than the second insulating film, and
wherein the first insulating film has less thickness variation than the second insulating film or the first insulating film has a more uniform thickness than the second insulating film.

15. The electronic device according to claim 1 , wherein the active layer includes an amorphous silicon semiconductor or an oxide semiconductor.

16. The electronic device according to claim 1 , wherein the transistor is disposed in an active area of the panel,
wherein a passivation layer covers a source electrode and a drain electrode of the transistor, and
wherein a pixel electrode is located on the passivation layer to be electrically connected to the source electrode or the drain electrode via a hole in the passivation layer.

17. The electronic device according to claim 1 , wherein each of a plurality of subpixels in an active area of the panel includes the transistor of claim 1 .

18. The electronic device according to claim 1 , wherein the transistor is included in a gate driver circuit disposed in a non-active area of the panel, in a periphery of the active area.

19. A transistor having a vertical structure, comprising:
a gate electrode disposed on a substrate;
a first insulating film disposed on the gate electrode;
an active layer disposed on the first insulating film, the active layer including:
a first portion of the active layer overlapping with an upper surface of the gate electrode,
a second portion of the active layer extending from the first portion, being disposed along a side surface of the gate electrode and including a channel area, and
a third portion of the active layer extending from the second portion, the third portion of the active layer being disposed on a portion of the first insulating film that does not overlap with the gate electrode;

a second insulating film disposed on the active layer;
a first electrode disposed on the second insulating film, the first electrode being electrically connected to the first portion of the active layer;
a second electrode disposed on the second insulating film, the second electrode being electrically connected to the third portion of the active layer; and
an insulation pattern disposed between the active layer and the second insulating film,
wherein the insulation pattern overlaps the channel area of the active layer.

20. The transistor according to claim 19 , wherein the side surface of the gate electrode has a reverse tapered shape, or the gate electrode has a stepped portion located in an area corresponding to the second portion of the active layer.

21. The transistor according to claim 19 , wherein the insulation pattern is disposed substantially parallel to the side surface of the gate electrode.

22. The transistor according to claim 19 , wherein the insulation pattern is disposed under a protruding portion or an eave portion of the active layer.

23. The transistor according to claim 22 , wherein the protruding portion or the eave portion of the active layer follows contours of a protruding portion of the first insulating layer, and
wherein the protruding portion of the first insulating layer follows contours of a protruding portion of the gate electrode.

24. The transistor according to claim 19 , wherein the channel area of the active layer is disposed substantially parallel to the side surface of the gate electrode.

Assignees

• Lg Display Co Ltd

Inventors

• Sung Sangyun
• Park Sehee
• Noh Jiyong
• Cho Intak
• Yun Pilsang

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6713

  characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes · CPC title

• H10D30/6704

  having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device · CPC title

• H10D10/40

  Vertical BJTs {(Vertical Heterojunction BJTs H10D10/821)} · CPC title

• H10D30/6728 Primary

  Vertical TFTs · CPC title