Embedded JFETs for high voltage applications

Patent metadata

Field	Value
Publication number	US-11069805-B2
Application number	US-201916704172-A
Country	US
Kind code	B2
Filing date	Dec 5, 2019
Priority date	May 25, 2012
Publication date	Jul 20, 2021
Grant date	Jul 20, 2021

Abstract

A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.

First claim

What is claimed is:

1. A device comprising:
a substrate;
a buried well region of a first conductivity type over the substrate;
a High Voltage Well (HVW) region of the first conductivity type over the buried well region;
an insulation region over the HVW region;
a drain region of the first conductivity type on a first side of the insulation region;
a gate electrode on a second side of the insulation region;
a well region adjacent to the insulation region, wherein the well region is of a second conductivity type opposite to the first conductivity type, and wherein the well region comprises a continuous portion, and a first leg connecting to the continuous portion; and
a first heavily doped region and a second heavily doped region of the first conductivity type in a top region of the HVW region, wherein the first heavily doped region and the second heavily doped region are separated from each other by the first leg.

2. The device of claim 1 , wherein the continuous portion and the gate electrode are on opposing sides of the first and the second heavily doped regions, and the first leg extends from the continuous portion in a direction toward the gate electrode.

3. The device of claim 1 further comprising:
a second leg connecting to the continuous portion, wherein the first leg and the second leg are separated from each other by the first heavily doped region; and
a third leg connecting to the continuous portion, wherein the first leg and the third leg are separated from each other by the second heavily doped region.

4. The device of claim 3 , wherein the continuous portion, the first leg, the second leg, and the third leg of the well region form a pattern of letter “E”.

5. The device of claim 3 , wherein the first leg and the second leg are further separated from each other by a portion of the HVW region.

6. The device of claim 1 , wherein the gate electrode is electrically shorted to the well region.

7. The device of claim 1 , wherein the first conductivity type is n-type.

8. The device of claim 1 , wherein the well region is configured to pinch off a current flowing through the buried well region.

9. The device of claim 1 further comprising a buried well layer between the first HVW region and the buried well region, wherein the buried well layer is of the second conductivity type.

10. A device comprising:
a buried n-type well (BNW) region;
a p-type buried layer (PBL) over and contacting the BNW region;
an high-voltage n-type well (HVNW) region comprising:
a first portion over and contacting the BNW region; and
a second portion over and contacting the PBL;

a p-well region over and contacting the BNW region, wherein the p-well region comprises a first leg and a second leg spaced apart from each other, and wherein the first leg and the second leg contact the PBL and the HVNW region; and
a first source region at top of the HVNW region, wherein the first source region is between the first leg and the second leg.

11. The device of claim 10 further comprising:
a second source region at top of the HVNW region, wherein the second source region is between the first leg and a third leg of the p-well region.

12. The device of claim 10 , wherein the p-well region comprises a continuous portion, with first ends of the first leg and the second leg joined with the continuous portion, and second ends of the first leg and the second leg are in contact with the PBL and the HVNW region.

13. The device of claim 10 further comprising:
a drain region on top of the first portion of the HVNW region; and
a heavily doped p-type region over and joined to the p-well region, wherein the first source region, the drain region, and the heavily doped p-type region in combination form a Junction Field-Effect Transistor (JFET).

14. The device of claim 10 , wherein a channel region of the JFET comprises an additional first portion in the BNW region, and an additional second portion in the HVNW region.

15. The device of claim 10 further comprising:
a gate dielectric over and contacting the HVNW region; and
a gate electrode over and contacting the gate dielectric, wherein the gate electrode is electrically connected to the p-well region.

16. A device comprising:
a Junction Field-Effect Transistor (JFET) comprising:
a high-voltage n-type well region (HVNW) region;
a drain region in the HVNW region;
an insulation region extending into the HVNW region;
a p-well region comprising a plurality of strip portions separated from each other, wherein first ends of the plurality of strip portions contact a sidewall of the HVNW region;
a first heavily doped n-type region and a second heavily doped n-type region extending into the HVNW region, wherein the first heavily doped n-type region and the second heavily doped n-type region are separated from each other by the plurality of strip portions of the p-well region; and
a heavily doped p-type region over and contacting the p-well region.

17. The device of claim 16 , wherein the p-well region further comprises an additional portion joining second ends of the plurality of strip portions.

18. The device of claim 16 , wherein the plurality of strip portions extend beyond opposing edges of both of the first heavily doped n-type region and the second heavily doped n-type region.

19. The device of claim 16 further comprising a p-type buried layer (PBL) underlying and contacting the HVNW region.

20. The device of claim 19 further comprising a buried n-type well region underlying and contacting the PBL.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yeh Jen-Hao
• Cheng Chih-Chang
• Su Ru-Yi
• Huo Ker Hsiao
• Chen Po-Chih
• Yang Fu-Chih
• Tsai Chun-Lin

Classifications

• H10D64/257

  for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D64/256

  for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D64/512

  Disposition of the gate electrodes, e.g. buried gates · CPC title

• H10D64/112

  comprising multiple field plate segments · CPC title

• H10D62/126 Primary

  Top-view geometrical layouts of the regions or the junctions · CPC title