Semiconductor device, method of manufacturing semiconductor device, inverter circuit, driving device, vehicle, and elevator

Patent metadata

Field	Value
Publication number	US-11069803-B2
Application number	US-202016797633-A
Country	US
Kind code	B2
Filing date	Feb 21, 2020
Priority date	Sep 13, 2019
Publication date	Jul 20, 2021
Grant date	Jul 20, 2021

Abstract

A semiconductor device according to an embodiment includes: a SiC layer having a first plane, a second plane, a first trench located on a first plane side, an n-type first SiC region, a p-type second SiC region between the first SiC region and the first plane, an n-type third SiC region between the second SiC region and the first plane, and a p-type fourth SiC region between the first SiC region and the first plane, at least a portion of the fourth SiC region located in the second SiC region, the fourth SiC region having a higher p-type impurity concentration than the second SiC region; a gate electrode in the first trench; a first electrode located on the first plane side; and a second electrode located on a second plane side. A depth of the fourth SiC region increases with distance from the first trench.

First claim

What is claimed is:

1. A semiconductor device comprising:
a silicon carbide layer having a first plane parallel to a first direction and a second direction perpendicular to the first direction and a second plane facing the first plane, the silicon carbide layer having
a first trench being located on a side of the first plane and extending in the first direction,
a first silicon carbide region of n-type,
a second silicon carbide region of p-type being located between the first silicon carbide region and the first plane,
a third silicon carbide region of n-type being located between the second silicon carbide region and the first plane, and
a fourth silicon carbide region of p-type being located between the first silicon carbide region and the first plane, at least a portion of the fourth silicon carbide region being located in the second silicon carbide region, the fourth silicon carbide region having a higher p-type impurity concentration than a p-type impurity concentration of the second silicon carbide region;
a gate electrode being located in the first trench;
a gate insulating layer being located between the gate electrode and the silicon carbide layer;
a first electrode being located on a side of the first plane of the silicon carbide layer; and
a second electrode being located on a side of the second plane of the silicon carbide layer,
wherein a first position and a second position exist in the at least portion of the fourth silicon carbide region, a first distance from the first plane to the first position is smaller than a second distance from the first plane to the second position, and a third distance from the gate insulating layer to the first position is smaller than a fourth distance from the gate insulating layer to the second position.

2. The semiconductor device according to claim 1 ,
wherein the first concentration distribution of the p-type impurity on a first virtual line including the first position and extending in the second direction has a first concentration peak at the first position, and
the second concentration distribution of the p-type impurity on a second virtual line including the second position and extending in the second direction has a second concentration peak at the second position.

3. The semiconductor device according to claim 1 , wherein an angle of a segment connecting the first position and the second position with respect to a normal line of the first plane is 20 degrees or more and 50 degrees or less.

4. The semiconductor device according to claim 1 , wherein the second silicon carbide region is located between the gate insulating layer and the fourth silicon carbide region.

5. The semiconductor device according to claim 1 , wherein the third distance is 0.05 μm or more, and the fourth distance is 0.5 μm or less.

6. The semiconductor device according to claim 1 , wherein the p-type impurity concentration at the first position and the p-type impurity concentration at the second position are 2 times or more and 100 times or less of the p-type impurity concentration of the second silicon carbide region near the gate insulating layer.

7. The semiconductor device according to claim 1 , wherein the fourth silicon carbide region is in contact with the third silicon carbide region.

8. The semiconductor device according to claim 7 , wherein the silicon carbide layer further includes a fifth silicon carbide region of n-type being located in the third silicon carbide region, the fifth silicon carbide region being located between the fourth silicon carbide region and the first plane, and the fifth silicon carbide region having an n-type impurity concentration lower than an n-type impurity concentration of the third silicon carbide region.

9. The semiconductor device according to claim 1 , wherein the fourth silicon carbide region is in contact with the first silicon carbide region.

10. The semiconductor device according to claim 1 , further comprising a second trench being located on a side of the first plane and extending in the first direction,
wherein a portion of the first electrode is located in the second trench, and
the fourth silicon carbide region is located between the first trench and the second trench.

11. The semiconductor device according to claim 10 , wherein the third distance is a half or less of a distance between the gate insulating layer and the second trench.

12. The semiconductor device according to claim 10 , wherein the silicon carbide layer further includes a sixth silicon carbide region of p-type being located between the second trench and the first silicon carbide region, and having a p-type impurity concentration higher than a p-type impurity concentration of the second silicon carbide region.

13. The semiconductor device according to claim 12 , wherein the fourth silicon carbide region is in contact with the sixth silicon carbide region.

14. An inverter circuit comprising the semiconductor device according to claim 1 .

15. A driving device comprising the semiconductor device according to claim 1 .

16. A vehicle comprising the semiconductor device according to claim 1 .

17. An elevator comprising the semiconductor device according to claim 1 .

18. A method of manufacturing a semiconductor device comprising:
forming a second silicon carbide region of p-type on a side of a first plane of a silicon carbide layer, the silicon carbide layer having a first plane, a second plane facing the first plane, and a first silicon carbide region of n-type located between the second plane and the first plane;
forming a third silicon carbide region of n-type between the second silicon carbide region and the first plane;
forming a mask material having an opening on a side of the first plane of the silicon carbide layer;
forming a fourth silicon carbide region of p-type by ion-implanting p-type impurities into the silicon carbide layer in a direction inclined at a first angle with respect to a normal line of the first plane by using the mask material as a mask, at least a portion of the fourth silicon carbide region being located in the second silicon carbide region;
forming a first trench on a side of the first plane of the silicon carbide layer;
forming a gate insulating layer in the first trench; and
forming a gate electrode on the gate insulating layer in the first trench,
wherein a first position and a second position exist in the at least a portion of the fourth silicon carbide region, a first distance from the first plane to the first position is smaller than a second distance from the first plane to the second position, and a third distance from the gate insulating layer to the first position is smaller than a fourth distance from the gate insulating layer to the second position.

19. The method of manufacturing a semiconductor device according to claim 18 , wherein before forming the fourth silicon carbide region, the first trench is formed.

20. The method of manufacturing a semiconductor device according to claim 18 , wherein a second trench is formed in the silicon carbide layer below the opening by etching the silicon carbide layer by using the mask material as a mask.

Assignees

• Toshiba Kk

Inventors

• Tanaka Katsuhisa
• Kyogoku Shinya
• Iijima Ryosuke
• Kimoto Shinichi

Classifications

• H10P30/2042 Primary

  into crystalline silicon carbide · CPC title

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10D30/0295

  using recessing of the source electrodes · CPC title

• H10D64/2527

  for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies · CPC title

• H10D30/0297

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title