Shift register unit, gate driving circuit, driving method and display apparatus

Patent metadata

Field	Value
Publication number	US-11069274-B2
Application number	US-201916497199-A
Country	US
Kind code	B2
Filing date	Apr 12, 2019
Priority date	Apr 26, 2018
Publication date	Jul 20, 2021
Grant date	Jul 20, 2021

Abstract

The embodiments of the present application provide a shift register unit and a method for driving the same, a gate driving circuit, and a display apparatus. Here, the shift register unit includes a first controlling sub-circuit, a first voltage dividing sub-circuit, a charging and discharging sub-circuit, and an outputting sub-circuit. Here, an output signal of the outputting sub-circuit is controlled by the charging and discharging sub-circuit. A first input signal and a second input signal input at a first input signal terminal Forward and a second input signal terminal Backward electrically coupled to the charging and discharging sub-circuit are pulse signals.

First claim

We claim:

1. A shift register circuit, comprising:
a first controlling sub-circuit configured to receive a first voltage signal and write the first voltage signal to a first node under a control of the first voltage signal, and receive a second voltage signal and write a second voltage signal to a second node under a control of the second voltage signal;
a first voltage dividing sub-circuit electrically coupled to the first controlling sub-circuit and an outputting signal terminal, and configured to receive a third voltage signal and an outputting signal from the outputting signal terminal, write the third voltage signal to the first node under a control of the outputting signal; and write the third voltage signal to the second node under the control of the outputting signal;
a charging and discharging sub-circuit electrically coupled to the first controlling sub-circuit, the first voltage dividing sub-circuit, a first inputting signal terminal and a second inputting signal terminal, and configured to receive a first clock signal, and write a first inputting signal from the first inputting signal terminal to a third node or receive a second inputting signal from the second inputting signal terminal to the third node, under a control of the first clock signal, a voltage at the first node, and a voltage at the second node; and an outputting sub-circuit electrically coupled to the charging and discharging sub-circuit and the outputting signal terminal, and configured to receive a second clock signal and output the second clock signal at the outputting signal terminal under a control of the voltage at the third node;
wherein the charging and discharging sub-circuit comprises a forward charging and discharging sub-circuit, and a reverse charging and discharging sub-circuit,
wherein the forward charging and discharging sub-circuit comprises a fifth transistor and a sixth transistor, wherein a gate of the fifth transistor is electrically coupled to a first clock signal terminal for providing a first clock signal, a first electrode of the fifth transistor is electrically coupled to the first inputting signal terminal, and a second electrode of the fifth transistor is electrically coupled to a first electrode of the sixth transistor; and a gate of the sixth transistor is electrically coupled to the first node, and a second electrode of the sixth transistor is electrically coupled to the third node; and
wherein the reverse charging and discharging sub-circuit comprises a seventh transistor and an eighth transistor, wherein a gate of the seventh transistor is electrically coupled to the first clock signal terminal, a first electrode of the seventh transistor is electrically coupled to the second inputting signal terminal, and a second electrode of the seventh transistor is electrically coupled to a first electrode of the eighth transistor; and
a gate of the eighth transistor is electrically coupled to the second node, and a second electrode of the eighth transistor is electrically coupled to the third node.

2. The shift register circuit of claim 1 , wherein the first controlling sub-circuit comprises a first transistor and a second transistor, wherein
a gate of the first transistor and a first electrode of the first transistor are electrically coupled to a first voltage signal terminal for providing the first voltage signal, and a second electrode of the first transistor is electrically coupled to the first node; and
a gate of the second transistor and a first electrode of the second transistor are electrically coupled to a second voltage signal terminal for providing the second voltage signal, and a second electrode of the second transistor is electrically coupled to the second node.

3. The shift register circuit of claim 1 , wherein the first voltage dividing sub-circuit comprises a third transistor and a fourth transistor,
wherein
a gate of the third transistor is electrically coupled to the outputting signal terminal, a first electrode of the third transistor is electrically coupled to the first node, and a second electrode of the third transistor is electrically coupled to a third voltage signal terminal for providing the third voltage signal; and
a gate of the fourth transistor is electrically coupled to the outputting signal terminal, a first electrode of the fourth transistor is electrically coupled to the second node, and a second electrode of the fourth transistor is electrically coupled to the third voltage signal terminal.

4. The shift register circuit of claim 1 , wherein the outputting sub-circuit comprises a first capacitor and a ninth transistor, wherein
a first electrode of the first capacitor is electrically coupled to the third node, and a second electrode of the first capacitor is electrically coupled to the outputting signal terminal; and
a gate of the ninth transistor is electrically coupled to the third node, a first electrode of the ninth transistor is electrically coupled to a second clock signal terminal for providing a second clock signal, and a second electrode of the ninth transistor is electrically coupled to the outputting signal terminal.

5. The shift register circuit of claim 1 , further comprising:
a first noise reduction sub-circuit configured to write the third voltage signal to the outputting signal terminal under the control of the voltage at the first node or the voltage at the second node.

6. The shift register circuit of claim 5 , wherein the first noise reduction sub-circuit comprises a tenth transistor and an eleventh transistor,
wherein
a gate of the tenth transistor is electrically coupled to the first node, a first electrode of the tenth transistor is electrically coupled to the outputting signal terminal, and a second electrode of the tenth transistor is electrically coupled to the third voltage signal terminal; and
a gate of the eleventh transistor is electrically coupled to the second node, a first electrode of the eleventh transistor is electrically coupled to the outputting signal terminal, and a second electrode of the eleventh transistor is electrically coupled to the third voltage signal terminal.

7. The shift register circuit of claim 1 , further comprising:
a second controlling sub-circuit configured to receive the first voltage signal and write the first voltage signal to a fourth node under the control of the first voltage signal; and receive the second voltage signal and write the second voltage signal to a fifth node under a control of the second voltage signal;
a second voltage dividing sub-circuit configured to receive a third voltage signal, write the third voltage signal to the fourth node under the control of the voltage at the third node, and write the third voltage signal to the fifth node under a control of the voltage at the third node; and
a second noise reduction sub-circuit configured to write the third voltage signal to the third node under a control of the voltage at the fourth node or a voltage at the fifth node.

8. A gate driving circuit, comprising:
N stages of shift register circuits according to claim 1 ;
wherein the first inputting signal terminal of the n th stage of shift register circuit is electrically coupled to the outputting signal terminal of the (n−1) th stage of shift register circuit, and the second inputting signal terminal of the n th stage of shift register circuit is electrically coupled to the outputting signal terminal of the (n+1) th stage of shift register circuit, N is an integer greater than or equal to 4, and n is an integer greater than 1 and less than N.

9. A display apparatus comprising the gate driving circuit of claim 8 .

10. A method for driving the shift register circuit of claim 1 , comprising:

Assignees

• Boe Technology Group Co Ltd

Inventors

• Wang Zhichong
• Han Seungwoo
• Shang Guangliang
• Zheng Haoliang
• Yuan Lijun
• Yao Xing
• Han Mingfu

Classifications

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G2310/0283

  Arrangement of drivers for different directions of scanning · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title