Shift register unit and driving method thereof, gate driving circuit and display device

Patent metadata

Field	Value
Publication number	US-11069271-B2
Application number	US-201816326434-A
Country	US
Kind code	B2
Filing date	Mar 7, 2018
Priority date	May 5, 2017
Publication date	Jul 20, 2021
Grant date	Jul 20, 2021

Abstract

Embodiments of the present disclosure provide a shift register unit and a driving method thereof, a gate driving circuit and a display device. The shift register unit comprises a shift register and a potential stabilizing circuit. The potential stabilizing circuit is configured to provide a signal from the reference signal terminal to the pulling-up node and the outputting signal terminal respectively, under a control of the potential stabilizing controlling terminal.

First claim

We claim:

1. A shift register unit, comprising:
a shift register comprising a pulling-up node, wherein the shift register is configured to output an outputting signal of an effective level at an outputting signal terminal under a control of a level at the pulling-up node; and
a potential stabilizing circuit configured to receive a potential stabilizing controlling signal from a potential stabilizing controlling signal terminal and provide a signal from a reference signal terminal to the pulling-up node and the outputting signal terminal respectively, under a control of the potential stabilizing controlling signal;
wherein the shift register comprises: a first controlling circuit, a second controlling circuit, and an outputting circuit, wherein
the first controlling circuit is configured to receive a first clock signal from a first clock signal terminal, and provide the first clock signal to a pulling-down node under a control of the first clock signal, and provide the signal from the reference signal terminal to the pulling-down node under the control of the level at the pulling-up node;
the second controlling circuit is configured to provide the signal from the reference signal terminal to the pulling-up node under a control of a level at the pulling-down node; and
the outputting circuit is configured to provide a second clock signal from a second clock signal terminal to the outputting signal terminal under the control of the level at the pulling-up node, maintain a difference between the level at the pulling-up node and a level at the outputting signal terminal in response to the pulling-up node being in a floating state, and provide the signal from the reference signal terminal to the outputting signal terminal under the control of the level at the pulling-down node.

2. The shift register unit of claim 1 , wherein the shift register further comprises: an inputting circuit, and a resetting circuit, wherein
the inputting circuit is configured to receive an inputting signal from an inputting signal terminal, and provide the inputting signal to the pulling-up node under a control of the inputting signal; and
the resetting circuit is configured to provide the signal from the reference signal terminal to the pulling-up node under a control of a signal from a resetting signal terminal.

3. The shift register unit of claim 2 , wherein the inputting circuit comprises: a third switching transistor having a controlling electrode and a first electrode both electrically coupled to the inputting signal terminal, and a second electrode electrically coupled to the pulling-up node;
the resetting circuit comprises: a fourth switching transistor having a controlling electrode electrically coupled to the resetting signal terminal, a first electrode electrically coupled to the reference signal terminal, and a second electrode electrically coupled to the pulling-up node;
the first controlling circuit comprises: a fifth switching transistor, a sixth switching transistor, a seventh switching transistor, and an eighth switching transistor, wherein the fifth switching transistor has a controlling electrode and a first electrode both electrically coupled to the first clock signal terminal, and a second electrode electrically coupled to a controlling electrode of the sixth switching transistor; the sixth switching transistor has a first electrode electrically coupled to the first clock signal terminal and a second electrode electrically coupled to the pulling-down node; the seventh switching transistor has a controlling electrode electrically coupled to the pulling-up node, a first electrode electrically coupled to the reference signal terminal, and a second electrode electrically coupled to the controlling electrode of the sixth switching transistor; the eighth switch transistor has a controlling electrode electrically coupled to the pulling-up node, a first electrode electrically coupled to the reference signal terminal, and a second electrode electrically coupled to the pulling-down node;
the second controlling circuit comprises: a ninth switching transistor having a controlling electrode electrically coupled to the pulling-down node, a first electrode electrically coupled to the reference signal terminal, and a second electrode electrically coupled to the pulling-up node; and
the outputting circuit comprises: a tenth switching transistor, an eleventh switching transistor, and a capacitor, wherein the tenth switching transistor has a controlling electrode electrically coupled to the pulling-up node, a first electrode electrically coupled to the second clock signal terminal, and a second electrode electrically coupled to the outputting signal terminal; the eleventh switching transistor has a controlling electrode electrically coupled to the pulling-down node, a first electrode electrically coupled to the reference signal terminal, and a second electrode electrically coupled to the outputting signal terminal; the capacitor has a first electrode electrically coupled to the pulling-up node and a second electrode electrically coupled to the outputting signal terminal.

4. A method for driving the shift register unit of claim 2 , comprising:
during a first period,
supplying, by the inputting circuit, the inputting signal to the pulling-up node under the control of the inputting signal; and
supplying, by the first controlling circuit, the signal from the reference signal terminal to the pulling-down node under the control of the level at the pulling-up node; and

during a second period,
supplying, by the outputting circuit, the second clock signal to the outputting signal terminal under the control of the level at the pulling-up node, and
maintaining the difference between the level at the pulling-up node and the level at the outputting signal terminal in response to the pulling-up node being in the floating state;

during a third period,
supplying, by the resetting circuit, the signal from the reference signal terminal to the pulling-up node under the control of the signal from the resetting signal terminal;
supplying, by the first controlling circuit, the first clock signal to the pulling-down node under the control of the first clock signal;
supplying, by the second controlling circuit, the signal from the reference signal terminal to the pulling-up node under the control of the level at the pulling-down node; and
supplying, by the outputting circuit, the signal from the reference signal terminal to the outputting signal terminal under the control of the level at the pulling-down node; and

during a fourth period,
supplying, by the potential stabilizing circuit, the signal from the reference signal terminal to the pulling-up node and the outputting signal terminal respectively, under the control of the potential stabilizing controlling signal.

5. A gate driving circuit comprising a plurality of shift register units according to claim 1 which are cascaded, wherein:
each of the shift register units other than the shift register unit in a last stage has the potential stabilizing controlling terminal electrically coupled to the pulling-down node of the shift register unit in a subsequent stage.

6. The gate driving circuit of claim 5 , wherein the shift register unit in a first stage has the inputting signal terminal electrically coupled to a frame triggering signal terminal;
each of the shift register units other than the shift register unit in the first stage has the inputting signal terminal electrically coupled to the outputting signal terminal of the shift register unit in a previous stage; and
each of the shift register units other than the shift register unit in the last stage has the resetting signal terminal electrically coupled to the outputting signal terminal of the shift register unit in t

Assignees

• Beijing Boe Display Tech Co
• Boe Technology Group Co Ltd

Inventors

• Gao Yingqiang
• Chen Huabin
• Liu Yang
• Zhou Ranyi

Classifications

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2320/0214

  with crosstalk due to leakage current of pixel switch in active matrix panels · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title