Control device and communication device

Patent metadata

Field	Value
Publication number	US-11068423-B2
Application number	US-201716478470-A
Country	US
Kind code	B2
Filing date	Nov 20, 2017
Priority date	Feb 7, 2017
Publication date	Jul 20, 2021
Grant date	Jul 20, 2021

Abstract

Provided is a control device that includes: a communication unit; one or more functional units; and a communication line connecting the communication unit and the one or the plurality of functional units. The communication unit includes: a computation processing unit in which a processor executes one or more tasks; a communication circuit which handles the transmission and reception of communication frames via the communication line; and a control circuit connected to the computation processing unit and the communication circuit. The control circuit includes: a first Direct Memory Access (DMA) core for accessing the computation processing unit; a second DMA core for accessing the communication circuit; and a controller which, in response to a trigger from the computation processing part, provides sequential commands to the first DMA core and the second DMA core in accordance with a predefined descriptor table.

First claim

What is claimed is:

1. A control device, comprising:
a communication unit;
one or a plurality of functional units; and
a communication line that has a plurality of channels independent of each other and connects the communication unit and the one or the plurality of functional units,
wherein the communication unit comprises:
an arithmetic processing part in which a processor executes one or a plurality of tasks;
a communication circuit that handles transmission and reception of communication frames via the communication line; and
a control circuit connected to the arithmetic processing part and the communication circuit,
wherein the control circuit comprises:
a first direct memory access (DMA) core for accessing the arithmetic processing part;
a second DMA core for accessing the communication circuit; and
a controller that gives commands to the first DMA core and the second DMA core sequentially according to a predefined descriptor table in response to a trigger from the arithmetic processing part; and
an activation unit configured to selectively activate a descriptor table designated from among a plurality of descriptor tables set with priorities different from each other in advance, wherein
in the arithmetic processing part, a plurality of tasks set with the priorities different from each other are executed, and
the communication unit is configured to execute
a first task of sending out, in a first cycle, a first communication frame for executing at least one of transmission of data collected by the functional units to the communication unit and transmission of data held by the communication unit to the functional units via a first channel among the plurality of channels and
a second task of sending out, in a second cycle different from the first cycle, a second communication frame for executing at least one of transmission of the data collected by the functional units to the communication unit and transmission of the data held by the communication unit to the functional units via a second channel among the plurality of channels, wherein the first task and the second task are among the plurality of tasks, and a priority of the first task is higher than a priority of the second task,
each of the plurality of descriptor tables is stored in the memory of the arithmetic processing part or the memory area of the control circuit according to a priority of the corresponding task, and
a descriptor table corresponding to the first task is stored in the memory area of the control circuit and a descriptor table corresponding to the second task is stored in the memory of the arithmetic processing part.

2. The control device according to claim 1 , wherein the control circuit further comprises an arbiter configured to arbitrate based on the priorities set in each of the descriptor tables when processings according to different descriptor tables are simultaneously requested.

3. The control device according to claim 1 , wherein each of the one or the plurality of functional units processes only any one of the communication frames in order to perform data exchange with the communication unit.

4. A communication device connected to one or a plurality of functional units via a communication line having a plurality of channels independent of each other, the communication device comprising:
an arithmetic processing part in which a processor executes one or a plurality of tasks;
a communication circuit that handles transmission and reception of communication frames via the communication line; and
a control circuit connected to the arithmetic processing part and the communication circuit,
wherein the control circuit comprises:
a first direct memory access (DMA) core for accessing the arithmetic processing part;
a second DMA core for accessing the communication circuit; and
a controller that gives commands to the first DMA core and the second DMA core sequentially according to a predefined descriptor table in response to a trigger from the arithmetic processing part; and
an activation unit configured to selectively activate a descriptor table designated from among a plurality of descriptor tables set with priorities different from each other in advance, wherein
in the arithmetic processing part, a plurality of tasks set with the priorities different from each other are executed, and, wherein
the communication device is configured to execute
a first task of sending out, in a first cycle, a first communication frame for executing at least one of transmission of data collected by the functional units to the communication device and transmission of data held by the communication device to the functional units via a first channel among the plurality of channels and
a second task of sending out, in a second cycle different from the first cycle, a second communication frame for executing at least one of transmission of the data collected by the functional units to the communication device and transmission of the data held by the communication device to the functional units via a second channel among the plurality of channels, wherein the first task and the second task are among the plurality of tasks, and a priority of the first task is higher than a priority of the second task,
each of the plurality of descriptor tables is stored in the memory of the arithmetic processing part or the memory area of the control circuit according to a priority of the corresponding task, and
a descriptor table corresponding to the first task is stored in the memory area of the control circuit and a descriptor table corresponding to the second task is stored in the memory of the arithmetic processing part.

Assignees

• Omron Tateisi Electronics Co

Inventors

• Takai Masaichi
• Nishimura Yasuhiro

Classifications

• H04L12/40019

  Details regarding a bus master · CPC title

• G05B2219/15056

  DMA · CPC title

• H04L12/28

  characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks] (wireless communication networks H04W {; arrangements for dividing the transmission path H04W40/00}) · CPC title

• G05B19/054

  Input/output · CPC title

• H04L12/40143

  involving priority mechanisms (hybrid switching fabrics H04L12/6402; intermediate storage or scheduling H04L49/90; time-division multiplex systems H04J3/00) · CPC title