Method and enable apparatus for starting physical device

Patent metadata

Field	Value
Publication number	US-11068348-B2
Application number	US-201916263800-A
Country	US
Kind code	B2
Filing date	Jan 31, 2019
Priority date	Oct 31, 2016
Publication date	Jul 20, 2021
Grant date	Jul 20, 2021

Abstract

This application discloses a method and an enable apparatus for starting a physical device, where the physical device includes N central processing units (CPUs) and at least one platform controller hub (PCH), N is greater than one. Each of the N CPUs is electrically coupled to a PCH in the at least one PCH. The method includes determining a second CPU in the N CPUs as the primary CPU when a fault occurs in a first CPU, where the first CPU is the primary CPU configured to start the physical device before the fault occurs in the first CPU, and triggering the second CPU as the primary CPU and in cooperation with a first PCH to start the physical device, where the first PCH is one PCH in the at least one PCH.

First claim

What is claimed is:

1. A method for starting a physical device, comprising:
detecting that a fault occurs in a first central processing unit (CPU) by an enable apparatus, wherein the enable apparatus is communicatively coupled to at least one platform control hub (PCH) and N CPUs, wherein the N is a positive integer greater than or equal to two, and wherein the N CPUs comprise the first CPU and a second CPU;
determining the second CPU in the N CPUs as a primary CPU when the fault occurs in the first CPU in the N CPUs, wherein the physical device comprises the N CPUs and the at least one PCH, wherein the first CPU is the primary CPU configured to start the physical device before the fault occurs in the first CPU, wherein an alternative CPU set comprises all CPUs of the N CPUs except the first CPU, and wherein determining the second CPU as the primary CPU comprises:
determining only one CPU in the alternative CPU set as the second CPU when the alternative CPU set comprises the only one CPU; and
determining, from P CPUs comprised in the alternative CPU set, one CPU as the second CPU when the alternative CPU set comprises the P CPUs, wherein the P is a positive integer greater than one, wherein determining, from the P CPUs comprised in the alternative CPU set, the one CPU as the second CPU comprises determining a CPU corresponding to an intermediate node in a serial link as the second CPU when the P CPUs in the alternative CPU set form the serial link, wherein the serial link comprises P nodes and P−1 sub-links, wherein the P CPUs are in a one-to-one correspondence with the P nodes, wherein the physical device further comprises P−1 electrical couplings among the P CPUs, wherein any one of the P CPUs are electrically coupled to at least one CPU of other CPUs of the P CPUs, and wherein the P−1 electrical couplings are in a one-to-one correspondence with the P−1 sub-links; and

sending an enable signal from the enable apparatus to the second CPU to trigger the second CPU as the primary CPU to, in cooperation with a first PCH, start the physical device, wherein the first PCH is electrically coupled to the second CPU, and wherein the first PCH is one of the at least one PCH.

2. The method of claim 1 , further comprising forbidding the first CPU to participate in starting of the physical device when the fault occurs in the first CPU.

3. The method of claim 1 , wherein the physical device comprises a first memory storing a basic input/output system (BIOS) program used for starting the physical device, and wherein starting the physical device in cooperation with the first PCH comprises accessing, by the second CPU, the first memory using the first PCH in order to execute the BIOS program.

4. The method of claim 3 , wherein the at least one PCH comprises a plurality of PCHs, wherein the physical device further comprises a chip selector electrically coupled to the PCHs and the first memory, and wherein before sending the enable signal from the enable apparatus to the second CPU to trigger the second CPU to start the physical device, the method further comprises instructing the chip selector to establish an electrical coupling between the first PCH and the first memory.

5. The method of claim 1 , wherein the physical device further comprises a data selector electrically coupled to each of the N CPUs and the first PCH, and wherein before sending the enable signal from the enable apparatus to the second CPU to trigger the second CPU to start the physical device, the method further comprises instructing the data selector to establish a communication coupling between the second CPU and the first PCH.

6. The method of claim 5 , wherein the data selector is communicatively coupled to the second CPU based on a first bus protocol and to the first PCH based on a second bus protocol and configured to:
convert data received from the second CPU and conforming to the first bus protocol into data conforming to the second bus protocol, and send the data conforming to the second bus protocol to the first PCH; or
convert data received from the first PCH and conforming to the second bus protocol into data conforming to the first bus protocol, and send the data conforming to the first bus protocol to the second CPU.

7. The method of claim 5 , wherein the data selector is communicatively coupled to the second CPU based on a first bus protocol and to the first PCH based on a second bus protocol and configured to:
convert data received from the second CPU and conforming to the first bus protocol into data conforming to the second bus protocol; and
send the data conforming to the second bus protocol to the first PCH.

8. The method of claim 5 , wherein the data selector is communicatively coupled to the second CPU based on a first bus protocol and to the first PCH based on a second bus protocol and configured to:
convert data received from the first PCH and conforming to the second bus protocol into data conforming to the first bus protocol; and
send the data conforming to the first bus protocol to the second CPU.

9. The method of claim 1 , wherein the at least one PCH comprises N PCHs, wherein the physical device further comprises N electrical couplings among the N CPUs and the N PCHs, wherein the N CPUs are in a one-to-one correspondence with the N PCHs, and wherein the second CPU is electrically coupled to the first PCH.

10. The method of claim 9 , wherein the physical device further comprises N memories and N electrical couplings among the N memories and the N PCHs, wherein the N memories are in a one-to-one correspondence with the N PCHs, and wherein the first memory is a memory of the N memories coupled to the first PCH.

11. The method of claim 1 , wherein the physical device comprises a server.

12. An enable apparatus for starting a physical device, comprising:
a non-transitory memory comprising instructions; and
a processor coupled to the non-transitory memory, wherein the instructions cause the processor to be configured to:
detect that a fault occurs in a first central processing unit (CPU) by the enable apparatus, wherein the enable apparatus is communicatively coupled to at least one platform control hub (PCH) and N CPUs, wherein the N is a positive integer greater than or equal to two, and wherein the N CPUs comprise the first CPU and a second CPU;
determine the second CPU in the N CPUs as a primary CPU when the fault occurs in the first CPU in the N CPUs, wherein the physical device comprises the N CPUs and the at least one PCH, wherein the first CPU is the primary CPU configured to start the physical device before the fault occurs in the first CPU, wherein an alternative CPU set comprises all CPUs of the N CPUs except the first CPU, and wherein the instructions further cause the processor to be configured to:
determine that only one CPU in the alternative CPU set is the second CPU when the alternative CPU set comprises the only one CPU; and
determine, from P CPUs comprised in the alternative CPU set, one CPU as the second CPU when the alternative CPU set comprises the P CPUs, wherein the P is a positive integer greater than one, wherein the instructions further cause the processor to be configured to determine a CPU corresponding to an intermediate node in a serial link as the second CPU when the P CPUs in the alternative CPU set form the serial link, wherein the serial link comprises P nodes and P−1 sub-links, wherein the P CPUs are in a one-to-one correspondence with the P nodes, wherein the physical device further comprises P−1 electrical couplings among the P CPUs, wherein any one of the P CPUs is electrically coupled to at least one CPU of other CPUs of the P CPUs, and wherein the P−1 electric

Assignees

• Huawei Tech Co Ltd

Inventors

• Chen Ben

Classifications

• G06F11/1438 Primary

  Restarting or rejuvenating · CPC title

• G06F11/0721 Primary

  within a central processing unit [CPU] · CPC title

• G06F11/1417 Primary

  Boot up procedures · CPC title

• G06F9/5072

  Grid computing · CPC title

• G06F11/2023

  Failover techniques · CPC title