Display device, liquid crystal display device, and organic EL display device

US11067864B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11067864-B2
Application numberUS-201916299194-A
CountryUS
Kind codeB2
Filing dateMar 12, 2019
Priority dateMar 16, 2018
Publication dateJul 20, 2021
Grant dateJul 20, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An embodiment of the present invention provides a display device which allows for the area of a wiring diverting region to be reduced. The display device (1) includes: a substrate (100) having a displaying region (30) and a non-displaying region (10); a plurality of first switching elements (TFT1, TFT2); a plurality of gate lines (50) each of which is respectively connected to a gate of one or more of the plurality of first switching elements; a plurality of second switching elements (TFT3); a plurality of sub gate lines (60) each of which is respectively connected to a gate of one or more of the plurality of second switching elements; and one or more connecting lines (70) each of which connects a respective one of the plurality of gate lines (50) to a respective one of the plurality of sub gate lines (60).

First claim

Opening claim text (preview).

The invention claimed is: 1. A display device comprising: a substrate having a displaying region and a non-displaying region; a plurality of first switching elements; a plurality of gate lines each of which is respectively connected to a gate of one or more of the plurality of first switching elements; a plurality of second switching elements; a plurality of sub gate lines each of which is respectively connected to a gate of one or more of the plurality of second switching elements; one or more connecting lines each of which connects a respective one of the plurality of gate lines to a respective one of the plurality of sub gate lines; one or more source lines; wherein the one or more connecting lines are provided in a layer differing from both (i) a layer in which the plurality of gate lines are provided an (ii) a layer in which the one or more source lines are provided. 2. The display device according to claim 1 , wherein the displaying region exists peripherally to at least a part of a perimeter of the non-displaying region. 3. The display device according to claim 1 , wherein: the substrate includes a wiring diverting region provided between the displaying region and the non-displaying region; and none of the plurality of sub gate lines exist in the wiring diverting region. 4. The display device according to claim 1 , wherein the layer in which the one or more connecting lines are provided includes one or more power supply lines to which an initialization voltage is applied. 5. The display device according to claim 1 , wherein each one of the one or more connecting lines connects one gate line, of the plurality of gate lines, to one sub gate line, of the plurality of sub gate lines, which one sub gate line is positioned downstream of the one gate line in terms of scan order. 6. A liquid crystal display device comprising the display device recited in claim 1 , wherein each of the plurality of second switching elements is connected to a respective one of a plurality of storage capacitors. 7. An organic EL display device comprising the display device recited in claim 1 , wherein each of the plurality of second switching elements is connected to a respective one of a plurality of wires to which a constant electric potential is supplied. 8. A display device comprising: a substrate having a displaying region and a non-displaying region; a plurality of first switching elements; a plurality of gate lines each of which is respectively connected to a gate of one or more of the plurality of first switching elements; a plurality of second switching elements; a plurality of sub gate lines each of which is respectively connected to a gate of one or more of the plurality of second switching elements; one or more connecting lines each of which connects a respective one of the plurality of gate lines to a respective one of the plurality of sub gate lines; one or more source lines; and a plurality of storage capacitor lines which are connected to each other via one or more common connecting lines. 9. The display device according to claim 8 , wherein the displaying region exists peripherally to at least a part of a perimeter of the non-displaying region. 10. The display device according to claim 8 , wherein: the substrate includes a wiring diverting region provided between the displaying region and the non-displaying region; and none of the plurality of sub gate lines exist in the wiring diverting region. 11. The display device according to claim 8 , wherein the one or more common connecting lines are positioned opposite to the non-display region with respect to corresponding one of the one or more collecting lines. 12. The display device according to claim 8 , wherein each one of the one or more connecting lines connects one gate line, of the plurality of gate lines, to one sub gate line, of the plurality of sub gate lines, which one sub gate line is positioned downstream of the one gate line in terms of scan order. 13. An organic EL display device comprising the display device recited in claim 8 , wherein each of the plurality of second switching elements is connected to a respective one of a plurality of wires to which a constant electric potential is supplied. 14. A display device comprising: a substrate having a displaying region and a non-displaying region; a plurality of first switching elements; a plurality of gate lines each of which is respectively connected to a gate of one or more of the plurality of first switching elements; a plurality of second switching elements; a plurality of sub gate lines each of which is respectively connected to a gate of one or more of the plurality of second switching elements; one or more connecting lines each of which connects a respective one of the plurality of gate lines to a respective one of the plurality of sub gate lines; and a reflective electrode layer; wherein the one or more connecting lines are provided in the reflective electrode layer. 15. The display device according to claim 14 , wherein the displaying region exists peripherally to at least a part of a perimeter of the non-displaying region. 16. The display device according to claim 14 , wherein: the substrate includes a wiring diverting region provided between the displaying region and the non-displaying region; and none of the plurality of sub gate lines exist in the wiring diverting region. 17. The display device according to claim 14 , wherein each one of the one or more connecting lines connects one gate line, of the plurality of gate lines, to one sub gate line, of the plurality of sub gate lines, which one sub gate line is positioned downstream of the one gate line in terms of scan order. 18. An organic EL display device comprising the display device recited in claim 14 , wherein each of the plurality of second switching elements is connected to a respective one of a plurality of wires to which a constant electric potential is supplied.

Assignees

Inventors

Classifications

  • integrated with passive devices, e.g. auxiliary capacitors · CPC title

  • adapted for preventing breakage, peeling or short circuiting · CPC title

  • H10D86/423Primary

    comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

  • wherein the TFTs are in active matrices · CPC title

  • Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

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What does patent US11067864B2 cover?
An embodiment of the present invention provides a display device which allows for the area of a wiring diverting region to be reduced. The display device (1) includes: a substrate (100) having a displaying region (30) and a non-displaying region (10); a plurality of first switching elements (TFT1, TFT2); a plurality of gate lines (50) each of which is respectively connected to a gate of one or …
Who is the assignee on this patent?
Sharp Kk
What technology area does this patent fall under?
Primary CPC classification H10D86/423. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 20 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).