Thermal compensation layers with core-shell phase change particles and power electronics assemblies incorporating the same

Patent metadata

Field	Value
Publication number	US-11067343-B2
Application number	US-201816170956-A
Country	US
Kind code	B2
Filing date	Oct 25, 2018
Priority date	Oct 25, 2018
Publication date	Jul 20, 2021
Grant date	Jul 20, 2021

Abstract

A thermal compensation layer includes a metal inverse opal (MIO) layer that includes a plurality of core-shell phase change (PC) particles encapsulated within a metal of the MIO layer. Each of the core-shell PC particles includes a core that includes a PCM having a PC temperature in a range of from 100° C. to 250° C., and a shell that includes a shell material having a melt temperature greater than the PC temperature of the PCM. A power electronics assembly includes a substrate having a thermal compensation layer formed proximate a surface of the substrate, the thermal compensation layer comprising an MIO layer that includes a plurality of core-shell PC particles encapsulated within a metal of the MIO layer. The power electronics assembly further includes an electronic device bonded to the thermal compensation layer at a first surface of the electronic device.

First claim

What is claimed is:

1. A thermal compensation layer comprising:
a metal inverse opal (MIO) layer that includes a plurality of core-shell phase change (PC) particles encapsulated within a metal of the MIO layer,
wherein each of the core-shell PC particles comprises:
a core comprising a phase change material (PCM) with a PC temperature in a range of from 100° C. to 250° C.; and
a shell comprising a shell material having a melt temperature greater than the PC temperature of the PCM,
wherein the PCM is tin or tin alloy.

2. The thermal compensation layer of claim 1 , further comprising a cap layer overgrown onto the MIO layer.

3. The thermal compensation layer of claim 1 , wherein the PCM comprises a paraffin or a metal.

4. The thermal compensation layer of claim 1 , further comprising a bonding layer in contact with the MIO layer, wherein the shell material has a melt temperature greater than a sintering temperature of the bonding layer.

5. The thermal compensation layer of claim 1 , wherein the shell material comprises a metal oxide or an electrically insulating polymer.

6. The thermal compensation layer of claim 1 , wherein the metal of the MIO layer comprises copper, nickel, aluminum, silver, zinc, magnesium, or alloys thereof.

7. The thermal compensation layer of claim 1 , wherein the MIO layer further comprises a plurality of hollow spheres that define a porosity of the MIO layer.

8. The thermal compensation layer of claim 1 , comprising a plurality of MIO layers, wherein each of the plurality of MIO layers includes a plurality of core-shell PC particles, wherein the PC temperature of the PCM in each of the MIO layers is different than a PC temperature of at least one other PCM of another of the plurality of MIO layers.

9. The thermal compensation layer of claim 1 , wherein the MIO layer is a first MIO layer having first core-shell PC particles with a first PCM in the core, and the thermal compensation layer further comprises a second MIO layer coupled to a surface of the first MIO layer, the second MIO layer comprising a plurality of second core-shell PC particles with a second PCM in the core, wherein the second PCM has a second PC temperature different than a first PC temperature of the first PCM.

10. A process for forming a thermal compensation layer, the process comprising:
depositing a plurality of core-shell PC particles onto a surface of a substrate or an electronic device, the plurality of core-shell PC particles comprising:
a core comprising a PCM with a PC temperature in a range of from 100° C. to 250° C.; and
a shell comprising a shell material having a melt temperature greater than the PC temperature of the PCM, wherein the PCM is tin or tin alloy;
depositing a metal over the plurality of core-shell PC particles to form an MIO layer; and overgrowing a cap layer on the MIO layer.

11. The process of claim 10 , wherein the MIO layer is a first MIO layer having first core-shell PC particles with a first PCM and the process further comprises:
depositing a plurality of second core-shell PC particles onto a surface of the first MIO layer, the second core-shell PC particles having a second PCM, wherein, a second PC temperature of the second PCM is different than a first PC temperature of the first PCM or an average particle size of the second core-shell PC particles is different than an average particles size of the first core-shell PC particles; and
electroplating metal over the plurality of second core-shell PC particles to form a second MIO layer.

12. A power electronics assembly comprising:
a substrate having a thermal compensation layer formed on an outer surface of the substrate, the thermal compensation layer comprising a metal inverse opal (MIO) layer and a cap layer on the MIO layer, the MIO layer including a plurality of core-shell phase change (PC) particles encapsulated within a metal of the MIO layer; and
an electronic device bonded to the thermal compensation layer at a first surface of the electronic device;
wherein each of the core-shell PC particles comprises:
a core comprising a phase change material (PCM) with a PC temperature in a range of from 100° C. to 250° C.; and
a shell comprising a shell material having a melt temperature greater than the PC temperature of the PCM.

13. The power electronics assembly of claim 12 , further comprising a bonding layer disposed between the thermal compensation layer and the electronic device.

14. The power electronics assembly of claim 12 , further comprising a supplemental thermal compensation layer bonded to the first surface or a second surface of the electronic device, the supplemental thermal compensation layer comprising a supplemental MIO layer having a plurality of supplemental core-shell PC particles encapsulated in a metal of the supplemental MIO layer.

15. The power electronics assembly of claim 12 , comprising a plurality of electronic devices, wherein the MIO layer is disposed at discrete locations of the bonding surface of the substrate, the discrete locations corresponding to locations at which each of the plurality of electronic devices are bonded to the substrate.

16. The power electronics assembly of claim 12 , wherein the MIO layer is a first MIO layer having first core-shell PC particles with a first PCM, and the thermal compensation layer further comprises a second MIO layer coupled to a surface of the first MIO layer, the second MIO layer comprising a plurality of second core-shell PC particles with a second PCM, wherein the second PCM has a PC temperature different than a PC temperature of the first PCM.

Assignees

• Toyota Eng & Mfg North America

Inventors

• Joshi Shailesh N
• Dede Ercan Mehmet

Classifications

• H10W40/735

  by melting or evaporation of solids · CPC title

• H10W40/70

  Fillings or auxiliary members in containers or in encapsulations for thermal protection or control · CPC title

• H10W40/73

  for cooling by change of state · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W72/381

  Auxiliary members · CPC title