Controller for a multi-phase converter and fault detection method thereof

Patent metadata

Field	Value
Publication number	US-11063508-B2
Application number	US-202016905320-A
Country	US
Kind code	B2
Filing date	Jun 18, 2020
Priority date	Jun 21, 2019
Publication date	Jul 13, 2021
Grant date	Jul 13, 2021

Abstract

A fault detection method for a multi-phase converter is: sampling currents flowing through a plurality of switching circuits to generate a plurality of current sampling signals; generating a plurality of digital current signals based on a plurality of current sampling signals; generating a plurality of on-time adjustment signals based on differences between each of the plurality of digital current signals and a reference current signal; averaging the plurality of on-time adjustment signals to generate an average adjustment signal; subtracting each of the plurality of on-time adjustment signals from the average adjustment signal to generate corresponding plurality of adjustment error signals; comparing each of the plurality of adjustment error signals with a threshold signal to generate a plurality of fault signals; and adjusting control signals of the plurality of switching circuits based on the plurality of fault signals.

First claim

We claim:

1. A controller for a multi-phase converter, wherein the multi-phase converter comprises a plurality of switching circuits coupled in parallel, the controller comprising:
an analog-to-digital conversion circuit, configured to receive a plurality of current sampling signals, and configured to generate a plurality of digital current signals based on the plurality of current sampling signals, wherein each of the plurality of current sampling signals respectively represents an associated current flowing through a corresponding one of the plurality of switching circuits;
an on-time adjustment signal generation circuit, coupled to the analog-to-digital conversion circuit to receive the plurality of digital current signals, and configured to generate a plurality of on-time adjustment signals based on differences between each of the plurality of digital current signals and a reference current signal, wherein each of the plurality of on-time adjustment signals represents an on-time adjustment of the corresponding one of the plurality of switching circuits;
a fault detection circuit, coupled to the on-time adjustment generation circuit to receive the plurality of on-time adjustment signals, and configured to generate a plurality of fault signals based on the plurality of on-time adjustment signals and a threshold signal; and
a control circuit, coupled to the fault detection circuit to receive the plurality of fault signals, and configured to generate a plurality of control signals based on the plurality of fault signals to control the plurality of switching circuits respectively.

2. The controller of claim 1 , wherein when a deviation between one of the plurality of on-time adjustment signals and an average adjustment signal exceeds the threshold signal, a corresponding one of the plurality of fault signals is configured to indicate that the corresponding one of the plurality of switching circuits is fault, and a corresponding control signal is configured to maintain the corresponding one of the plurality of switching circuits off, wherein the average adjustment signal represents an average of the on-time adjustments of the plurality of switching circuits.

3. The controller of claim 1 , further comprising:
a precision adjustment circuit, coupled between the on-time adjustment signal generation circuit and an averaging circuit, and configured to extract a high Q-bit of the plurality of on-time adjustment signals as a plurality of second on-time adjustment signals, wherein the plurality of on-time adjustment signals are configured to be P-bit, P is greater than or equal to Q, and the plurality of second on-time adjustment signals are configured to be transmitted to the averaging circuit as the plurality of on-time adjustment signals.

4. The controller of claim 1 , further comprising:
a precision adjustment circuit, coupled between the on-time adjustment signal generation circuit and an averaging circuit, configured to convert the plurality of on-time adjustment signals into corresponding plurality of high-precision on-time adjustment signals, wherein the plurality of on-time adjustment signals are configured to be P-bit, and the corresponding plurality of high-precision on-time adjustment signals are configured to be S-bit, S is greater than P, and the corresponding plurality of high-precision on-time adjustment signals are transmitted to the averaging circuit as the plurality of on-time adjustment signals.

5. The controller of claim 1 , wherein the on-time adjustment signal generation circuit further comprises:
a plurality of subtractors, wherein each of the plurality of subtractors comprises a first input terminal, a second input terminal, and an output terminal, the first input terminal of each of the plurality of subtractors is configured to receive the reference current signal, the second input terminal of each of the plurality of subtractors is configured to receive a corresponding one of the plurality of digital current signals, and the output terminal of each of the plurality of subtractors is configured to provide a corresponding one of the plurality of on-time adjustment signals via subtracting the reference current signal from the corresponding one of the plurality of digital current signals.

6. The controller of claim 5 , wherein the on-time adjustment signal generation circuit further comprises:
a plurality of proportional integrators, each of the plurality of proportional integrators comprises an input terminal and an output terminal, wherein the input terminal of each of the plurality of proportional integrators is coupled to the output terminal of a corresponding one of the plurality of subtractors to receive the corresponding one of the plurality of on-time adjustment signals, and the output terminal of each of the plurality of proportional integrators is configured to provide an integration signal as the corresponding one of the plurality of on-time adjustment signals.

7. The controller of claim 1 , wherein the fault detection circuit further comprises:
an averaging circuit, coupled to the on-time adjustment signal generation circuit to receive the plurality of on-time adjustment signals, and configured to generate an average adjustment signal by averaging the plurality of on-time adjustment signals;
a plurality of subtractors, coupled to the on-time adjustment signal generation circuit to receive the plurality of on-time adjustment signals, coupled to the averaging circuit to receive the average adjustment signal, and configured to subtract each of the plurality of on-time adjustment signals from the average adjustment signal to generate a plurality of adjustment error signals; and
a plurality of comparators, coupled to the plurality of subtractors to receive the plurality of adjustment error signals, and configured to compare each of the plurality of adjustment error signals with the threshold signal to generate the plurality of fault signals; wherein
when an absolute value of one of the plurality of adjustment error signals is greater than the threshold signal, a corresponding one of the plurality of fault signals is configured to indicate that the corresponding one of the plurality of switching circuits is fault.

8. The controller of claim 7 , wherein the averaging circuit further comprises:
an adder, comprising a plurality of input terminals and an output terminal, wherein the plurality of input terminals of the adder is configured to receive the plurality of on-time adjustment signals, and the output terminal of the adder is configured to provide an adjustment sum signal via summing the plurality of on-time adjustment signals; and
a divider, comprising a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the divider is configured to receive the adjustment sum signal, the second input terminal of the divider is configured to receive a phase number signal representative of a number of the plurality of switching circuits, and the output terminal of the divider is configured to provide the average adjustment signal via dividing the adjustment sum signal by the phase number signal.

9. A fault detection method for a multi-phase converter, wherein the multi-phase converter comprises a plurality of switching circuits coupled in parallel, the fault detection method comprising:
generating a plurality of digital current signals based on a plurality of current sampling signals, wherein each of the plurality of current sampling signals respectively represents an associated current flowing through a corresponding one of the plurality of switching circuits;
generating a plurality of on-time adjustment signals based on differences between each of the plurality of digital cu

Assignees

• Chengdu Monolithic Power Sys

Inventors

• Lu Wenbin
• Hu Wangmiao
• Jiang Lijie

Classifications

• H02M3/1584 Primary

  with a plurality of power processing stages connected in parallel · CPC title

• H02M1/0009

  Devices or circuits for detecting current in a converter · CPC title

• H02M1/32 Primary

  Means for protecting converters other than automatic disconnection · CPC title

• H02M1/08

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

• H02M1/325

  with means for allowing continuous operation despite a fault, i.e. fault tolerant converters · CPC title