Display device comprising thin film transistors and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-11063103-B2
Application number	US-201916666869-A
Country	US
Kind code	B2
Filing date	Oct 29, 2019
Priority date	Nov 7, 2018
Publication date	Jul 13, 2021
Grant date	Jul 13, 2021

Abstract

A display device includes a substrate, a pixel driver on the substrate, and a display element connected to the pixel driver. The pixel driver includes a conductive layer on the substrate, a buffer layer on the conductive layer, a semiconductor layer on the buffer layer, a gate electrode, the gate electrode overlapping the semiconductor layer, and a source electrode and a drain electrode connected to the semiconductor layer. The buffer layer includes a flattened portion overlapping the conductive layer, and a stepped portion overlapping the periphery of the conductive layer. The semiconductor layer includes a first oxide semiconductor layer on the buffer layer, and a second oxide semiconductor layer on the first oxide semiconductor layer. A width of the first oxide semiconductor layer is larger than a width of the second oxide semiconductor layer, and the first oxide semiconductor layer is on the stepped portion of the buffer layer.

First claim

What is claimed is:

1. A display device, comprising:
a substrate;
a pixel driver on the substrate; and
a display element connected to the pixel driver,
wherein the pixel driver includes:
a conductive layer on the substrate;
a buffer layer on the conductive layer;
a semiconductor layer on the buffer layer;
a gate electrode, at least a part of the gate electrode overlapping at least a part of the semiconductor layer; and
a source electrode and a drain electrode respectively connected to the semiconductor layer,

wherein the buffer layer includes a flattened portion overlapping the conductive layer, and a stepped portion overlapping the periphery of the conductive layer,
wherein the semiconductor layer includes a first oxide semiconductor layer on the buffer layer, and a second oxide semiconductor layer on the first oxide semiconductor layer,
wherein a width of the first oxide semiconductor layer is larger than a width of the second oxide semiconductor layer, and
wherein at least a portion of the first oxide semiconductor layer is on the stepped portion of the buffer layer.

2. The display device according to claim 1 , wherein the second oxide semiconductor layer is on the flattened portion of the buffer layer.

3. The display device according to claim 1 , wherein the first oxide semiconductor layer extends from the flattened portion of the buffer layer to the stepped portion of the buffer layer.

4. The display device according to claim 1 , wherein the first oxide semiconductor layer includes gallium (Ga), and a concentration of gallium (Ga) in the first oxide semiconductor layer is higher than a concentration of gallium (Ga) in the second oxide semiconductor layer.

5. The display device according to claim 4 , wherein the first oxide semiconductor layer includes gallium (Ga) of 50 atom % or more than 50 atom % based on total metallic element of the first oxide semiconductor layer with respect to number of atoms.

6. The display device according to claim 1 , wherein an etching rate of the first oxide semiconductor layer is lower than an etching rate of the second oxide semiconductor layer under the same etching conditions.

7. The display device according to claim 1 , wherein a width of the first oxide semiconductor layer is relatively larger by 0.2 μm˜5 μm in comparison to a width of the second oxide semiconductor layer.

8. The display device according to claim 1 , wherein a width of the first oxide semiconductor layer is larger than a width of the conductive layer.

9. The display device according to claim 1 , wherein the first oxide semiconductor layer has a thickness of 5 nm˜25 nm.

10. The display device according to claim 1 , wherein the conductive layer is a light blocking layer.

11. The display device according to claim 1 , wherein the conductive layer is a wiring configured to supply a signal to the pixel driver.

12. The display device according to claim 1 , wherein the semiconductor layer, the gate electrode, the source electrode, and the drain electrode constitute a driving thin film transistor configured to control a driving voltage applied to the display element.

13. A method for manufacturing a display device, comprising:
forming a conductive layer on a substrate;
forming a buffer layer on the conductive layer;
forming a first oxide semiconductor material layer and a second oxide semiconductor material layer on the buffer layer;
forming a semiconductor layer by patterning the first oxide semiconductor material layer and the second oxide semiconductor material layer; and
forming a gate insulating film and a gate electrode on the semiconductor layer,
wherein a width of the first oxide semiconductor layer is larger than a width of the second oxide semiconductor layer; and
wherein at least a portion of the first oxide semiconductor layer is disposed on a stepped portion of the buffer layer.

14. The method according to claim 13 , wherein the first oxide semiconductor material layer and the second oxide semiconductor material layer are formed by metal-organic chemical vapor deposition (MOCVD).

15. The method according to claim 13 , wherein a concentration of gallium in the first oxide semiconductor material layer is higher than a concentration of gallium in the second oxide semiconductor material layer.

16. The method according to claim 13 , wherein the first oxide semiconductor material layer includes gallium (Ga) of 50 atom % or more than 50 atom % based on total metallic element of the first oxide semiconductor material layer with respect to number of atoms.

17. The method according to claim 13 , wherein the first oxide semiconductor material layer has a thickness of 5 nm˜25 nm.

Assignees

• Lg Display Co Ltd

Inventors

• Seo Jungseok
• Yun Pilsang
• Park Sehee
• Noh Jiyong

Classifications

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D30/6713

  characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes · CPC title

• H10D30/6704

  having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device · CPC title

• H10D86/40

  characterised by multiple TFTs · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title