Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11063062-B2
Application number	US-201916564783-A
Country	US
Kind code	B2
Filing date	Sep 9, 2019
Priority date	Mar 11, 2019
Publication date	Jul 13, 2021
Grant date	Jul 13, 2021

Abstract

In one embodiment, a semiconductor device includes a first chip and a second chip. The first chip includes a first substrate, a control circuit provided on the first substrate, and a first pad provided above the control circuit and electrically connected to the control circuit. The second chip includes a second pad provided on the first pad, a plug provided above the second pad, extending in a first direction, and including a portion that decreases in diameter in a cross-section perpendicular to the first direction with increasing distance from the first substrate, and a bonding pad provided on the plug, intersecting with the first direction, and electrically connected to the second pad by the plug.

First claim

The invention claimed is:

1. A semiconductor device comprising a first chip and a second chip, wherein
the first chip comprises:
a first substrate;
a control circuit provided on the first substrate;
a first pad provided above the control circuit and electrically connected to the control circuit; and
a third pad provided above the control circuit and electrically connected to the control circuit, and

the second chip comprises:
a second pad provided on the first pad;
a plug provided above the second pad, extending in a first direction, and including a portion that decreases in diameter in a cross-section perpendicular to the first direction with increasing distance from the first substrate;
a bonding pad provided on the plus, intersecting with the first direction, and electrically connected to the second pad by the plug;
a fourth pad provided on the third pad; and
a memory cell array electrically connected to the fourth pad.

2. The device of claim 1 , wherein
the second chip further includes an insulator provided on the bonding pad, and
the insulator includes an opening to expose an upper face of the bonding pad.

3. The device of claim 2 , wherein the opening is provided at a position where the opening overlaps with the plug in the first direction.

4. The device of claim 1 , wherein
a memory cell array in the second chip includes a plurality of electrode layers stacked separately from one another in the first direction,
an end portion of the plug on a side of the first chip is provided at a position lower than a lower face of a lowermost one of the plurality of electrode layers, and
an end portion of the plug on a side opposite to the first chip is provided at a position higher than an upper face of an uppermost one of the plurality of electrode layers.

5. The device of claim 1 , wherein the plug has a tapered side face.

6. The device of claim 1 , wherein the second chip comprises a plurality of plugs between the second pad and the bonding pad.

7. The device of claim 1 , wherein the bonding pad is provided on the plug via no substrate.

8. A semiconductor device comprising a first chip and a second chip, wherein
the first chip comprises:
a first substrate;
a control circuit provided on the first substrate; and
a first pad provided above the control circuit and electrically connected to the control circuit, and

the second chip comprises:
a second pad provided on the first pad;
a plug provided above the second pad, extending in a first direction, and including a portion that decreases in diameter in a cross-section perpendicular to the first direction with increasing distance from the first substrate;
a bonding pad provided on the plug, intersecting with the first direction, and electrically connected to the second pad by the plug; and
an insulator provided on the bonding pad and including an opening to expose an upper face of the bonding pad, the opening being provided at a position where the opening does not overlap with the plug in the first direction.

9. The device of claim 8 , wherein the opening is provided at a position where the opening overlaps with a memory cell array inside the second chip in the first direction.

Assignees

• Toshiba Memory Corp

Inventors

• Iijima Jun
• Tagami Masayoshi
• Arai Shinya
• Tomimatsu Takahiro

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/722

  between stacked chips · CPC title