Stacking structure having material layer on graphene layer and method of forming material layer on graphene layer

Patent metadata

Field	Value
Publication number	US-11062818-B2
Application number	US-201514588734-A
Country	US
Kind code	B2
Filing date	Jan 2, 2015
Priority date	Jan 3, 2014
Publication date	Jul 13, 2021
Grant date	Jul 13, 2021

Abstract

Example embodiments relate to a stacking structure having a material layer formed on a graphene layer, and a method of forming the material layer on the graphene layer. In the stacking structure, when the material layer is formed on the graphene layer by using an ALD method, an intermediate layer as a seed layer may be formed on the graphene layer by using a linear type precursor.

First claim

What is claimed is:

1. An electronic device comprising;
a source electrode;
a drain electrode;
a channel layer formed between the source electrode and the drain electrode, the channel layer including graphene;
an intermediate layer formed on the channel layer, the intermediate layer being directly in contact with the channel layer;
a gate insulating layer formed on the intermediate layer; and
a gate electrode formed on the gate insulating layer;
wherein the intermediate layer includes at least one of Ge oxide, Ni oxide, Fe oxide and Sn oxide;
wherein the gate insulating layer comprises a material having a dielectric constant greater than a dielectric constant of Si, or one of Al oxide, Ti oxide, Hf oxide, W oxide, Ta oxide, Ru oxide, Zr oxide, and Zn oxide,
wherein the intermediate layer act as a seed layer making the gate insulating layer have physical stability, and
wherein the intermediate layer is formed on the channel layer from a linear type precursor, the linear type precursor comprises at least one of diethylzinc, (Be(N(SiMe 3 ) 2 ) 2 , Co(N(SiEtMe 2 ) 2 ) 2 , Fe(N(SiMe 3 ) 2 ) 2 , Ge(NtBu 2 ) 2 , Ge(NtBuSiMe 3 ) 2 , Ni(N(SiMe 3 ) 2 ) 2 , and Sn(NtBuSiMe 3 ) 2 .

2. The electronic device of claim 1 , wherein the intermediate layer has a thickness in a range of about 0.1 nm to about 5 nm.

3. A method of forming an electronic device, the method comprising:
forming a source electrode, a drain electrode, a channel layer formed between the source electrode and the drain electrode, the channel layer including graphene;
forming an intermediate layer that is a board-shaped thin layer lying on a surface of the channel layer by using a linear type precursor, the intermediate layer including at least one of Ge oxide, Ni oxide, Fe oxide and Sn oxide and being directly in contact with the channel layer;
forming a gate insulating layer on the intermediate layer by using an ALD method, the gate insulating layer comprising a material having a dielectric constant greater than a dielectric constant of Si, or at least one of Al oxide, Ti oxide, Hf oxide, W oxide, Ta oxide, Ru oxide, Zr oxide, and Zn oxide wherein the intermediate layer act as a seed layer making the gate insulating layer have physical stability, and
wherein the linear type precursor comprises at least one of diethylzinc, (Be(N(SiMe 3 ) 2 ) 2 , Co(N(SiEtMe 2 ) 2 ) 2 , Fe(N(SiMe 3 ) 2 ) 2 , Ge(NtBu 2 ) 2 , Ge(NtBuSiMe 3 ) 2 , Ni(N(SiMe 3)2)2 , and Sn(NtBuSiMe 3)2 .

4. The method of claim 3 , wherein the intermediate layer has a thickness in a range of about 0.1 nm to about 5 nm.

Assignees

• Samsung Electronics Co Ltd
• Sungkyunkwan Univ Research & Business Foundation

Inventors

• Jeong Seong-Jun
• Park Seong-Jun
• Shin Hyeon-Jin
• Gu Yea-Hyun
• Kim Hyoung-Sub
• Yang Jae-Hyun

Classifications

• H10D30/6741

  Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755) · CPC title

• H10D30/01

  Manufacture or treatment · CPC title

• H10D30/6739

  Conductor-insulator-semiconductor electrodes · CPC title

• H10D62/882

  Graphene · CPC title

• H10D64/685 Primary

  being perpendicular to the channel plane · CPC title