Display device having a gate driver in a non-display area having a curved portion

Patent metadata

Field	Value
Publication number	US-11062657-B2
Application number	US-201916503077-A
Country	US
Kind code	B2
Filing date	Jul 3, 2019
Priority date	Oct 22, 2015
Publication date	Jul 13, 2021
Grant date	Jul 13, 2021

Abstract

A display device includes a display panel having a curved side or a polygonal side, the display panel including a plurality of pixels in a display region, a gate driver including a plurality of normal stages connected to each other for outputting gate signals to the pixels via a plurality of gate lines, and a plurality of dummy stages between some of the normal stages, and a data driver providing data signals to the pixels via a plurality of data lines.

First claim

What is claimed is:

1. A display device comprising:
a plurality of pixels in a display region in which an image is displayed;
a plurality of gate lines comprising a first gate line and a second gate line;
a plurality of data lines crossing the first and second gate lines; and
a gate driver in a non-display region adjacent to the display region, wherein at least a portion of the non-display region has a curved shape in a plan view, and
wherein the gate driver comprises:
a first gate driver having an output terminal which is electrically connected to the first gate line; and
a second gate driver having an output terminal which is electrically connected to the second gate line, and

wherein the display device further comprises a circuit portion located between the first gate driver and the second gate driver, the circuit portion having an output terminal which is floated,
wherein the circuit portion having the floated output terminal has an input terminal and a first clock terminal, and the input terminal and the first clock terminal are electrically connected to a same signal line.

2. The display device of claim 1 , wherein the circuit portion further has a second clock terminal, and
wherein the input terminal, the first clock terminal and the second clock terminal of the circuit portion are electrically connected to the same signal line.

3. The display device of claim 1 , wherein the output of the circuit portion is not electrically connected to any of the pixels nor another gate driver.

4. The display device of claim 1 , further comprising a data driver in the non-display region, the data driver being electrically connected to the data line.

5. The display device of claim 1 , wherein the circuit portion comprises a dummy gate driver.

6. The display device of claim 1 , wherein the circuit portion comprises a plurality of circuit portions, and wherein the number of the circuit portions located at a first side of the second gate driver is different from the number of the circuit portions located at a second side of the second gate driver which is opposite to the first side.

7. A display device comprising:
a plurality of pixels in a display region in which an image is displayed,
first and second gate lines;
a data line crossing the gate lines; and
a gate driver in a non-display region adjacent to the display region, wherein at least a portion of the non-display region has a curved shape,
wherein the gate driver comprises:
a first gate driver electrically connected to the first gate line; and
a second gate driver electrically connected to the second gate line, and

wherein the display device further comprises:
a circuit portion located between the first gate driver and the second gate driver, the circuit portion comprising an input terminal, a first clock terminal and second clock terminal, wherein the input terminal, the first clock terminal and the second clock terminal of the circuit portion are electrically connected to a same signal line.

8. The display device of claim 7 , wherein the circuit portion further comprises:
a first power terminal configured to receive a first gate voltage; and
a second power terminal configured to receive a second gate voltage.

9. The display device of claim 8 , wherein the circuit portion comprises:
a first input transistor connected between the input terminal and a first node and having a gate electrode connected to the second clock terminal;
a first stabilizing transistor connected between the first power terminal and a second stabilizing transistor and having a gate electrode connected to a third node;
the second stabilizing transistor connected between the first stabilizing transistor and the first node and having a gate electrode connected to the first node;
a second input transistor connected between the third node and the second clock terminal and having a gate electrode connected to the first node;
a holding transistor connected between the third node and a second power terminal and having a gate electrode connected to the second clock terminal;
a first output transistor connected between the first clock terminal and an output terminal and having a gate electrode connected to a second node;
a second output transistor connected between the first power terminal and the output terminal and having a gate electrode connected to the third node;
a first capacitor connected between the first power terminal and the third node;
a second capacitor connected between the second node and the output terminal; and
a node control transistor connected between the first node and the second node and having a gate node connected to the second power terminal.

10. The display device of claim 7 , wherein the circuit portion comprises a dummy gate driver.

11. The display device of claim 7 , wherein the circuit portion comprises a plurality of circuit portions, and wherein the number of the circuit portion located at a first side of the second gate driver is different from the number of the circuit portions located at a second side of the second gate driver which is opposite to the first side.

12. The display device of claim 7 , wherein an output terminal of the circuit portion is electrically floated.

13. A display device comprising:
a plurality of pixels in a display region in which an image is displayed,
first and second gate lines;
a data line crossing the gate lines; and
a gate driver in a non-display region adjacent to the display region, wherein at least a portion of the non-display region has a curved shape,
wherein the gate driver comprises:
a first gate driver having an input terminal to receive a vertical start signal; and
a second gate driver having an input terminal which is electrically connected to an output terminal of the first gate driver, and

wherein the display device further comprises a circuit portion located between the first gate driver and the second gate driver, and has an input terminal to receive a constant voltage.

14. The display device of claim 13 , wherein each of first and second gate drivers and the circuit portion further comprises:
a first power terminal configured to receive a first gate voltage; and
a second power terminal configured to receive a second gate voltage.

15. The display device of claim 14 , wherein the constant voltage to be received by the input terminal of the circuit portion is the first gate voltage.

16. The display device of claim 13 , wherein the circuit portion comprises a dummy gate driver.

17. The display device of claim 13 , wherein the circuit portion comprises a plurality of circuit portions, and wherein the number of the circuit portion located at a first side of the second gate driver is different from the number of the circuit portions located at a second side of the second gate driver which is opposite to the first side.

Assignees

• Samsung Display Co Ltd

Inventors

• Bae Jung-Bae
• Lee So-Young
• Lee Won-Se

Classifications

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G09G2310/0264

  Details of driving circuits · CPC title

• G09G3/3275

  Details of drivers for data electrodes · CPC title

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title