Instructions controlling access to shared registers of a multi-threaded processor

Patent metadata

Field	Value
Publication number	US-11061680-B2
Application number	US-201514847157-A
Country	US
Kind code	B2
Filing date	Sep 8, 2015
Priority date	Oct 28, 2014
Publication date	Jul 13, 2021
Grant date	Jul 13, 2021

Abstract

Atomic instructions, including a Compare And Swap Register, a Load and AND Register, and a Load and OR Register instruction, use registers instead of storage to communicate and share information in a multi-threaded processor. The registers are accessible to multiple threads of the multi-threaded processor, and the instructions operate on these shared registers. Access to the shared registers is controlled by the instructions via interlocking.

First claim

What is claimed is:

1. A computer-implemented method of facilitating control in a multi-threaded processor, said computer-implemented method comprising:
obtaining, by the multi-threaded processor, a first instruction to be executed to perform a first operation and a second instruction to be executed to perform a second operation, the first instruction being initiated by a first thread of the multi-threaded processor and the second instruction being initiated by a second thread of the multi-threaded processor;
initiating execution, by the multi-threaded processor, of the first instruction to perform the first operation and the second instruction to perform the second operation, the first operation and the second operation each comprising multiple sub-operations to be performed atomically, wherein the first instruction enters a first pipeline and the second instruction enters a second pipeline;
determining, by the multi-threaded processor, whether the first instruction and the second instruction are to continue to execute, the determining using interlocking to determine whether the first instruction or the second instruction has atomic access to one or more registers shared by the first thread, the second thread, and one or more other threads of the multi-threaded processor, wherein the one or more registers are accessed by multiple threads during execution of instructions and comprise one or more hardware registers separate from memory of the multi-threaded processor, and wherein the interlocking is to control inter-thread and intra-thread operations by guaranteeing atomicity with accesses to the one or more registers shared by the first thread, the second thread, and the one or more other threads, wherein the first thread, the second thread, and the one or more other threads can each individually freely write the one or more registers, wherein the determining is based on utilizing a register to generate a random number to select, based on a most significant bit of the random number either the first pipeline or the second pipeline to set an interlock, wherein the interlock comprises a value placed in a hardware register accessible to the multiple threads, in order to provide the atomic access to the one or more registers to the first instruction or the second instruction;
continuing execution, by the multi-threaded processor, of the first instruction based on the interlocking indicating the first instruction is to execute, the continuing execution comprising performing the first operation including using at least one shared register of the one or more registers shared by the first thread, the second thread, and the one or more other threads of the multi-threaded processor to perform the first operation;
rejecting execution, by the multi-threaded processor, of the second instruction based on the interlocking indicating a prior instruction has atomic access to the one or more registers; and
re-executing, by the multi-threaded processor, the second instruction, at completion of execution of the first instruction.

2. The computer-implemented method of claim 1 , wherein the first instruction comprises a compare and swap register instruction.

3. The computer-implemented method of claim 1 , wherein the first instruction comprises a load and AND register instruction.

4. The computer-implemented method of claim 1 , wherein the first instruction comprises a load and OR register instruction.

Assignees

• IBM

Inventors

• Biran Giora
• Busaba Fadi Y
• Erez Ophir
• Farrell Mark S
• Heller Lisa C
• Jacobi Christian
• Mesh Alexander
• Slegel Timothy J

Classifications

• G06F9/30021 Primary

  Compare instructions, e.g. Greater-Than, Equal-To, MINMAX · CPC title

• G06F9/3851

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06F2209/521

  Atomic · CPC title

• G06F9/3004

  to perform operations on memory · CPC title

• G06F9/544

  Buffers; Shared memory; Pipes · CPC title