Memory device and method of operating the same

Patent metadata

Field	Value
Publication number	US-11061616-B2
Application number	US-201916729183-A
Country	US
Kind code	B2
Filing date	Dec 27, 2019
Priority date	May 17, 2019
Publication date	Jul 13, 2021
Grant date	Jul 13, 2021

Abstract

The present technology relates to a memory device and a method of operating the memory device. The memory device includes a target block manager configured to store a target block address on which a refresh operation is to be performed and output a refresh signal for the target block corresponding to the target block address when an auto refresh command is received, and a data transmission controller configured to output a transmission signal and a buffer control signal for transmitting data between the target block or the buffer block and the temporary buffer circuit in response to the refresh signal.

First claim

What is claimed is:

1. A memory device comprising:
a target block capable of storing data;
a buffer block capable of temporarily storing the data of the target block during a refresh operation of the target block;
a temporary buffer circuit configured to temporarily store or output the data of the target block or the buffer block in response to a buffer control signal;
a target block manager configured to store a target block address of the target block on which the refresh operation is to be performed and output a refresh signal for the target block corresponding to the target block address when an auto refresh command is received;
a data transmission controller configured to output a first transmission signal or a second transmission signal and the buffer control signal for transmitting the data between the target block or the buffer block and the temporary buffer circuit in response to the refresh signal;
a block erase controller configured to output a first erase signal and the buffer control signal for erasing the target block when the data of the target block is transmitted from the temporary buffer circuit to the buffer block and configured to output a second erase signal and the buffer control signal for erasing the buffer block when the data of the target block is transmitted from the temporary buffer circuit to the target block; and
an operation circuit configured to transmit read, program, or erase operation voltages to the target block or the buffer block in response to the first or second transmission signal or the first or second erase signal.

2. The memory device according to claim 1 , wherein the target block manager stores the target block address corresponding to the target block, and updates the target block address with an address of a next target block when the refresh operation of the target block has ended.

3. The memory device according to claim 2 , wherein the target block manager stores and updates a target page address corresponding to a target page on which the refresh operation is to be performed among a plurality of pages included in the target block.

4. The memory device according to claim 1 , wherein the data transmission controller outputs a first transmission end signal after outputting the first transmission signal and the buffer control signal so that the data is transmitted from the target block to the temporary buffer circuit and the data is transmitted from the temporary buffer circuit to the buffer block, in response to the refresh signal, and outputs a second transmission end signal after outputting the second transmission signal and the buffer control signal so that the data is transmitted from the buffer block to the temporary buffer circuit and the data is transmitted from the temporary buffer circuit to the target block, when an erase end signal is received from the block erase controller.

5. The memory device according to claim 4 , wherein the block erase controller outputs the first erase signal for erasing the target block in response to the first transmission end signal and outputs the second erase signal for erasing the buffer block in response to the second transmission end signal.

6. The memory device according to claim 5 , wherein the block erase controller outputs the erase end signal to the data transmission controller when an erase operation of the target block has ended and outputs an address count signal to the target block manager when an erase operation of the buffer block has ended.

7. The memory device according to claim 6 , wherein the target block manager updates the target block address with the address of a next target block and ends the refresh operation, when the address count signal is received.

8. The memory device according to claim 1 , wherein the operation circuit outputs the read operation voltages for transmitting the data from the target block to the temporary buffer circuit and outputs the program operation voltages for transmitting the data stored in the temporary buffer circuit to the buffer block, in response to the first transmission signal.

9. The memory device according to claim 1 , wherein the operation circuit outputs the read operation voltages for transmitting the data from the buffer block to the temporary buffer circuit and outputs the program operation voltages for transmitting the data stored in the temporary buffer circuit to the target block, in response to the second transmission signal.

10. The memory device according to claim 1 , wherein the operation circuit outputs the erase operation voltages for erasing the target block in response to the first erase signal and outputs the erase operation voltages for erasing the buffer block in response to the second erase signal.

11. The memory device according to claim 1 , wherein, when a plurality of pieces of logical page data is stored in a target page included in the target block, the temporary buffer circuit includes a plurality of latches for storing the plurality of pieces of logical page data, respectively.

12. The memory device according to claim 11 , wherein the temporary buffer circuit transmits the plurality of respective pieces of logical page data included in the latches to pages included in the buffer block.

13. The memory device according to claim 1 , wherein at least one of memory blocks is set as the buffer block.

14. The memory device according to claim 13 , when a plurality of planes each of which includes a plurality of memory blocks are included in the memory device, the buffer block is set to each of the planes or set in at least one plane among the planes.

15. A memory device comprising:
a target block capable of storing data;
a buffer block capable of temporarily storing the data of the target block during a refresh operation of the target block;
a temporary buffer circuit configured to temporarily store or output the data of the target block or the buffer block in response to a buffer control signal;
a target block manager configured to store and update a target block address of the target block on which the refresh operation is to be performed and repeatedly output a refresh signal for the target block corresponding to an updated target block address until a refresh end command is received, when a self refresh command is received;
a data transmission controller configured to output a first transmission signal or a second transmission signal and the buffer control signal for transmitting the data between the target block or the buffer block and the temporary buffer circuit in response to the refresh signal;
a block erase controller configured to output a first erase signal and the buffer control signal for erasing the target block when the data of the target block is transmitted from the temporary buffer circuit to the buffer block and configured to output a second erase signal and the buffer control signal for erasing the buffer block when the data of the target block is transmitted from the temporary buffer circuit to the target block; and
an operation circuit configured to transmit read, program, or erase operation voltages to the target block or the buffer block in response to the first or second transmission signal or the first or second erase signal.

16. The memory device according to claim 15 , wherein the target block manager repeatedly outputs the refresh signal until the refresh end command is received when the self refresh command is received.

17. The memory device according to claim 15 , wherein the target block manager stores the updated target block address and ends the refresh operation when the refres

Assignees

• Sk Hynix Inc

Inventors

• Choi Won Jae
• Gwon Ki Chang

Classifications

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title