Component carrier comprising a photo-imageable dielectric and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11058009-B2
Application number	US-201916689511-A
Country	US
Kind code	B2
Filing date	Nov 20, 2019
Priority date	Nov 20, 2018
Publication date	Jul 6, 2021
Grant date	Jul 6, 2021

Abstract

A method of manufacturing a component carrier is disclosed. The method includes forming a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure; patterning a front side of the stack using a first photo-imageable dielectric; and patterning a back side of the stack. A component carrier is also disclosed.

First claim

The invention claimed is:

1. A method of manufacturing a component carrier, comprising:
forming a stack comprising at least one electrically conductive layer structure and at least one electrically insulating layer structure;
patterning a front side of the stack using a first photo-imageable dielectric;
patterning a back side of the stack;
providing a metal or metallized core;
attaching a temporary carrier on a backside of the metal or metallized core;
forming a first cavity into the metal or metallized core;
embedding a semiconductor chip and/or a passive component into the first cavity;
applying the first photo-imageable dielectric on a front side of the metal or metallized core;
patterning the first photo-imageable dielectric at the first cavity for contacting the embedded semiconductor chip and/or the passive component, thereby forming holes on the front side;
removing the temporary carrier from the backside of the metal or metallized core;
applying a dielectric on a backside of the metal or metallized core;
patterning the dielectric on the backside at the first cavity, thereby forming holes on the back side; and
plating or filling the holes by a metal.

2. The method according to claim 1 , wherein patterning the front side of the stack using a first photo-imageable dielectric comprises illumination with electromagnetic radiation through a mask, followed by developing of the illuminated first photo-imageable dielectric, followed in turn by a selective removal of either the illuminated portion or the non-illuminated portion of the developed first photo-imageable dielectric.

3. The method according to claim 1 , wherein the first photo-imageable dielectric is patterned for contacting embedded components having different distances between the front side and an upper main surface of the respective component.

4. The method according to claim 1 , further comprising:
patterning the back side of the stack by laser drilling.

5. The method according to claim 1 , wherein a through-hole composed of a first hole portion with straight sidewalls on the front side connected to a second hole portion with tapering sidewalls on the backside is formed.

6. The method according to claim 1 , wherein patterning the front side of the stack using the first photo-imageable dielectric comprises forming multiple holes on the front side with different vertical depths.

7. The method according to claim 1 , wherein patterning the back side of the stack comprises forming multiple holes on the back side with substantially the same vertical depth.

8. The method according to claim 1 , wherein patterning the front side of the stack using the first photo-imageable dielectric comprises forming multiple holes on the front side with different horizontal widths.

9. The method according to claim 1 , further comprising:
forming a wire and/or a coax cable in a hole or a via or of the component carrier.

10. The method according to claim 1 , wherein a metal or metallized core is provided, to which the first photo-imageable dielectric is applied.

11. The method according to claim 1 , wherein forming the stack comprises forming a dielectric core with metallized sidewalls.

12. The method according to claim 1 , wherein forming the stack comprises forming a through-hole formed by the first photo-imageable dielectric on the front side, by a dielectric on the backside, and by laser processing from the backside.

13. The method according to claim 12 , wherein the dielectric on the backside is a thermal curing material or a second photo-imageable dielectric.

14. The method according to claim 1 , wherein before patterning the dielectric on the backside at the first cavity, at least one metal layer is applied onto the backside of the metal or metallized core, the metal layer is patterned, and the dielectric is applied on the at least one patterned metal layer.

15. The method according to claim 1 , further comprising:
forming a second cavity into the metal or metallized core;
patterning the first photo-imageable dielectric at the second cavity, thereby forming holes on the front side;
patterning the dielectric on the backside at the second cavity, thereby forming holes on the back side; and
plating or filling the holes by a metal.

16. A component carrier, comprising:
a stack comprising at least one electrically conductive layer structure and/or at least one electrically insulating layer structure;
at least one hole with straight sidewalls on a front side of the stack;
at least one hole with tapering sidewalls on a back side of the stack;
a cured patterned first photo-imageable dielectric on the front side of the stack;
at least one cone-shaped hole on the back side of the stack;
a metal or metallized core having a first cavity, in which a semiconductor chip and/or a passive component is accommodated; and
a through-hole passing through the metal or metallized core of the component carrier;
wherein the through-hole extending from the front side has sidewalls being at least partially covered with the cured first photo-imageable dielectric;
wherein an inner surface of the through-hole is plated or filled by a metal;
wherein the semiconductor chip or the passive component are mounted on a second photo-imageable dielectric on the back side of the stack or embedded in first photo-imageable dielectric.

17. The component carrier according to claim 16 , further comprising at least one of the following features:
the at least one electrically conductive layer structure comprises at least one of the group consisting of copper, aluminum, nickel, silver, gold, palladium, and tungsten;
the at least one electrically insulating layer structure comprises at least one of the group consisting of resin, reinforced or non-reinforced resin, epoxy resin or Bismaleimide-Triazine resin, FR-4, FR-5, cyanate ester, polyphenylene derivate, glass, prepreg material, polyimide, polyamide, liquid crystal polymer, epoxy-based Build-Up Film, polytetrafluoroethylene, a ceramic, and a metal oxide;
the component carrier is shaped as a plate;
the component carrier is configured as one of the group consisting of a printed circuit board, and a substrate;
the component carrier is configured as a laminate-type component carrier.

18. The component carrier of claim 16 , further comprising:
at least one cone-shaped hole on the front side of the stack;
wherein an inner surface of the at one cone-shaped hole on the front side of the stack is plated or filled with a metal.

19. The component carrier of claim 18 , wherein the plated or filled cone-shaped hole on the front side of the stack contacts at least one of the passive component or the metal or metallized core.

20. A component carrier, comprising:
a stack comprising at least one electrically conductive layer structure and at least one electrically insulating layer structure;
a cured patterned first photo-imageable dielectric on a front side of the stack;
at least one cone-shaped hole on a back side of the stack;
a metal or metallized core having a first cavity, in which a semiconductor chip or a passive component is accommodated;
a through-hole passing through the metal or metallized core of the component carrier;
wherein the through-hole extends from the front side of the stack and has sidewalls being at least partially covered with the cured first photo-imageable dielectric;
wherein an inner surface of the through-hole is plated or filled by a metal;
wherein the semiconductor chip or the passive compone

Assignees

• At & S Austria Tech & Systemtechnik Ag

Inventors

• Mok Jeesoo

Classifications

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W70/614

  the multiple chips being integrally enclosed · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title