Semiconductor device having three-dimensional structure and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11056485-B2
Application number	US-201916595379-A
Country	US
Kind code	B2
Filing date	Oct 7, 2019
Priority date	Dec 18, 2018
Publication date	Jul 6, 2021
Grant date	Jul 6, 2021

Abstract

A semiconductor device having a three-dimensional structure is disclosed herein. The semiconductor device includes a substrate. a first electrode line that extends in a first direction perpendicular to the substrate, a device pattern that extends from the first electrode line in a second direction parallel to the substrate, and a second electrode line connected to the device pattern. The device pattern may comprise at least one semiconductor layer pattern, where the at least one semiconductor layer pattern comprises an n-type dopant or a p-type dopant.

First claim

What is claimed is:

1. A semiconductor device having a three-dimensional structure, semiconductor device comprising:
a substrate;
a first electrode line extending in a first direction perpendicular to the substrate;
a device pattern extending from the first electrode line in a second direction parallel to the substrate; and
a second electrode line connected to the device pattern,
wherein the device pattern comprises at least one semiconductor layer pattern, the at least one semiconductor layer pattern comprising an n-type dopant or a p-type dopant, and
wherein the second electrode line extends in a third direction that is not parallel to the first electrode line.

2. The semiconductor device of claim 1 ,
wherein the first electrode line comprises:
an inner pillar structure; and
an outer wall layer surrounding the inner pillar structure.

3. The semiconductor device of claim 2 ,
wherein the outer wall layer comprises a semiconductor material, and
wherein the inner pillar structure comprises a conductive material having lower resistivity than the outer wall layer.

4. The semiconductor device of claim 1 ,
wherein the device pattern is formed of a semiconductor layer pattern that was doped to form a p-type or n-type semiconductor layer pattern.

5. The semiconductor device of claim 1 ,
wherein the device pattern comprises a first semiconductor layer pattern that was doped to form a p-type semiconductor layer pattern and a second semiconductor pattern that was doped to form an n-type semiconductor layer pattern.

6. The semiconductor device of claim 1 ,
wherein the device pattern comprises a first semiconductor layer pattern that was doped to form a p-type semiconductor layer pattern, a second semiconductor layer pattern that was doped to form an n-type semiconductor layer pattern, a third semiconductor layer pattern that was doped to form a p-type semiconductor layer pattern and a fourth semiconductor layer pattern that was doped to form an n-type semiconductor layer pattern, which are sequentially disposed along the device pattern, or comprises a first semiconductor layer pattern that was doped to form an n-type semiconductor layer pattern, a second semiconductor layer pattern that was doped to form a p-type semiconductor layer pattern, a third semiconductor layer pattern that was doped to form an n-type semiconductor layer pattern and a fourth semiconductor layer pattern that was doped to form an p-type semiconductor layer pattern, which are sequentially disposed along the device pattern.

7. The semiconductor device of claim 1 ,
wherein the second electrode line is parallel to the substrate and extends in the third direction perpendicular to the second direction.

8. A semiconductor device having a three-dimensional structure, the semiconductor device comprising:
a substrate;
first electrode lines extending in a first direction perpendicular to the substrate;
device patterns and interlayer insulating layers, which are alternately stacked on the substrate in the first direction; and
second electrode lines disposed on the same plane as the device patterns,
wherein the device patterns extend from the first electrode lines in a second direction parallel to the substrate and are connected to the second electrode lines, each of the device patterns comprising at least one doped semiconductor layer pattern, and
wherein the second electrode lines extend in a third direction that is not parallel to the first electrode lines.

9. The semiconductor device of claim 8 ,
wherein the second electrode lines are parallel to the substrate and extend to the third direction perpendicular to the second direction.

10. The semiconductor device of claim 9 ,
wherein the first electrode lines are arranged spaced apart from each other along a third direction that is parallel to the substrate and perpendicular to the second direction.

11. The semiconductor device of claim 10 , further comprising:
insulating patterns isolating the device patterns adjacent to each other along the third direction, and extending in the second direction.

12. The semiconductor device of claim 10 ,
wherein each of the first electrode lines comprises:
an inner pillar structure; and
an outer wall layer surrounding the inner pillar structure,
the inner pillar structure comprising a conductive material having lower resistivity than the outer wall layer.

13. The semiconductor device of claim 12 ,
wherein each of the device patterns comprises a diode device pattern doped to form a p-type diode device pattern or an n-type diode device pattern.

14. The semiconductor device of claim 12 ,
wherein each of the device patterns comprises a plurality of semiconductor layer patterns having at least one pn junction from the first electrode lines to the second electrode lines.

Assignees

• Sk Hynix Inc

Inventors

• Kim Hae Ri
• You Tae Jun
• Song Ju Ry

Classifications

• H10P14/416

  of highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title

• H10P14/412

  Deposition of metallic or metal-silicide materials · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D88/01

  Manufacture or treatment · CPC title

• H10D18/01

  Manufacture or treatment · CPC title