Chip-on-film package, display panel, and display device

Patent metadata

Field	Value
Publication number	US-11056027-B2
Application number	US-201916692122-A
Country	US
Kind code	B2
Filing date	Nov 22, 2019
Priority date	Feb 10, 2017
Publication date	Jul 6, 2021
Grant date	Jul 6, 2021

Abstract

A chip-on-film package includes a base substrate on which a first pad region, a second pad region, and a third region located between the first pad region and the second pad region are defined, a dummy pad disposed on the first pad region, input pads disposed on the first pad region, output pads disposed on the second region, a first detection line disposed on the base substrate, and a second detection line disposed on the base substrate. The first detection line is connected to a first input pad and a second input pad via the second pad region to form a first loop between the first input pad and the second input pad, and the second detection line is connected to the dummy pad and the first detection line via the third region to form a second loop between the dummy pad and the first input pad.

First claim

What is claimed is:

1. A chip-on-film package comprising:
a base substrate on which a first pad region extends on a first side defining one side of the base substrate, a second pad region extending on a second side defining an opposite side of the base substrate to the one side of the base substrate, and a third region located between the first pad region and the second pad region are defined;
a dummy pad disposed on the first pad region;
a plurality of input pads disposed on the first pad region;
a plurality of output pads disposed on the second pad region;
a first detection line disposed on the base substrate, wherein the first detection line includes a first sub-detection line connected between a first input pad of the input pads and a first output pad of the output pads, a second sub-detection line connected between a second input pad of the input pads and a second output pad of the output pads, a third sub-detection line connected between the second sub-detection line and a third output pad of the output pads, a fourth sub-detection line connected between a third input pad of the input pads and a fourth output pad of the output pads, and a fifth sub-detection line connected between a fourth input pad of the input pads and the fourth sub-detection line, the first output pad being connected to the third output pad in the second pad region, and the second output pad being connected to the fourth output pad in the second pad region,
a second detection line disposed on the base substrate, wherein the second detection line is connected between the dummy pad and the first sub-detection line.

2. The chip-on-film package of claim 1 , wherein the first output pad is connected to the third output pad through a first short pad in the second pad region.

3. The chip-on-film package of claim 1 , wherein the second output pad is connected to the fourth output pad through a second short pad in the second pad region.

4. The chip-on-film package of claim 1 , wherein the second detection line is connected to the first sub-detection line in the third region.

5. The chip-on-film package of claim 1 , wherein the third sub-detection line is connected to the second sub-detection line in the third region.

6. The chip-on-film package of claim 1 , wherein the fifth sub-detection line is connected to the fourth sub-detection line in the third region.

7. The chip-on-film package of claim 1 , wherein the dummy pad comprises an alignment key for alignment of the input pads.

8. The chip-on-film package of claim 1 , wherein the second detection line comprises a detection pattern disposed on the third region in a zigzag pattern.

9. The chip-on-film package of claim 1 , wherein the dummy pad is located in outermost among the input pads.

10. The chip-on-film package of claim 1 , further comprising:
an integrated circuit chip connected to the dummy pad and the input pads.

Assignees

• Samsung Display Co Ltd

Inventors

• Lee Hee-Kwon
• Hong Seungkyun

Classifications

• H10W74/129

  forming a chip-scale package [CSP] · CPC title

• H10W70/688

  Flexible insulating substrates · CPC title

• H10W20/484

  Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes · CPC title

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title