Systems and methods for disjoint character set report merging

Patent metadata

Field	Value
Publication number	US-11055257-B2
Application number	US-201715590492-A
Country	US
Kind code	B2
Filing date	May 9, 2017
Priority date	May 9, 2017
Publication date	Jul 6, 2021
Grant date	Jul 6, 2021

Abstract

The present disclosure relates to systems and methods for automatically optimizing a reporting architecture of an application. In one implementation, a system for automatically optimizing a reporting architecture of an application may include a memory storing instructions and an automata processor configured to execute the instructions. The instructions may include identifying one or more state transition elements in the application; determining if two or more state transition elements have disjoint character sets; grouping two or more state transition elements having disjoint character sets into one or more groups; merging state transition elements included in the one or more groups; and outputting a merged report configured for disambiguation on a second processor.

First claim

What is claimed is:

1. A system for automatically optimizing automata graphs for applications on spatial reconfigurable automata processors, comprising:
a memory storing instructions; and
an automata processor configured to execute the instructions to:
identify one or more state transition elements in the application;
determine if two or more state transition elements have disjoint character sets;
group two or more state transition elements having disjoint character sets into one or more groups;
activate one or more state transition elements in response to a Damerau-Levenshtein distance of a global input and the one or more state transition element being less than a threshold;
merge activation states of the state transition elements included in the one or more groups; and
output a merged report configured for disambiguation on a second processor.

2. The system of claim 1 , wherein the instructions to merge state transition elements comprise installing OR gates configured to combine two or more reports from state transition elements included in the one or more groups.

3. The system of claim 1 , wherein the instructions to merge state transition elements comprise adding one or more child elements to the one or more groups configured to combine two or more reports from state transition elements included in the one or more groups.

4. The system of claim 1 , wherein the instructions to merge state transition elements comprise wiring the outputs of at least one group of the one or more groups to a single report port of the automata processor.

5. The system of claim 1 , wherein the automata processor comprises one or more field-programmable gate arrays.

6. The system of claim 1 , wherein the automata processor comprises a Micron Automata Processor.

7. A method for automatically optimizing automata graphs for applications on a spatial reconfigurable automata processor, comprising:
identifying one or more state transition elements in the application;
determining if two or more state transition elements have disjoint character sets;
grouping two or more state transition elements having disjoint character sets into one or more groups;
activating one or more state transition elements in response to a Jaccard index of a global input and the one or more state transition element exceeding a threshold;
merging activation states of the state transition elements included in one or more groups; and
outputting a merged report configured for disambiguation on a second processor.

8. The method of claim 7 , wherein merging state transition elements comprises installing OR gates configured to combine two or more reports from state transition elements included in the one or more groups.

9. The method of claim 7 , wherein merging state transition elements comprises adding one or more child elements to the one or more groups configured to combine two or more reports from state transition elements included in the one or more groups.

10. The system of claim 1 , wherein merging state transition elements comprises wiring the outputs of at least one group of the one or more groups to a single report port of the automata processor.

11. A method for automatically disambiguating a merged report from an application on automata processor, comprising:
determining if a group of state transition elements in the application having disjoint character sets has been activated by a triggering input based on a comparison between a threshold and a Damerau-Levenshtein distance of a global input and at least one state transition element of the group;
receiving the triggering input;
determining which set of the disjoint character sets matches the triggering input; and
disambiguating the report based on the set matching the triggering input.

Assignees

• Univ Virginia Patent Foundation

Inventors

• Wadden John Pierson
• Angstadt Kevin Alan

Classifications

• G06F15/76 Primary

  Architectures of general purpose stored program computers (with program plugboard G06F15/08; multicomputers G06F15/16) · CPC title

• G06F15/80

  comprising an array of processing units with common control, e.g. single instruction multiple data processors (G06F15/82 takes precedence {; for correlation function computation G06F17/15}) · CPC title

• G06F15/7867 Primary

  with reconfigurable architecture · CPC title