Reordering of data for parallel processing

Patent metadata

Field	Value
Publication number	US-11050682-B2
Application number	US-201715719081-A
Country	US
Kind code	B2
Filing date	Sep 28, 2017
Priority date	Sep 28, 2017
Publication date	Jun 29, 2021
Grant date	Jun 29, 2021

Abstract

A network interface device, including: an ingress interface; a host platform interface to communicatively couple to a host platform; and a packet preprocessor including logic to: receive via the ingress interface a data sequence including a plurality of discrete data units; identify the data sequence as data for a parallel processing operation; reorder the discrete data units into a reordered data frame, the reordered data frame configured to order the discrete data units for consumption by the parallel operation; and send the reordered data to the host platform via the host platform interface.

First claim

What is claimed is:

1. A network interface device, comprising:
an ingress interface;
a host platform interface to communicatively couple to a host platform; and
a packet preprocessor comprising logic to:
receive via the ingress interface a data sequence comprising a plurality of discrete data units;
identify the data sequence as data for a parallel processing operation;
reorder the discrete data units into a reordered data frame, the reordered data frame configured to order the discrete data units for consumption by the parallel operation; and
send the reordered data to the host platform via the host platform interface.

2. The network interface of claim 1 , wherein the data sequence is a single data packet.

3. The network interface of claim 2 , wherein reordering the discrete data units comprises segmenting the reordered data frame into a plurality of buffers.

4. The network interface of claim 1 , wherein the data sequence comprises a plurality of packets, and wherein reordering comprises coalescing the plurality of packets and the reordered data frame comprises a single buffer.

5. The network interface of claim 1 , wherein the packet preprocessor is further to send the data sequence to the host platform.

6. The network interface of claim 1 , wherein the packet preprocessor is to provide the reordered data frame with metadata identifying the data frame as ready for consumption by the parallel processing operation.

7. The network interface of claim 1 , further comprising a vector switch to switch the reordered data frame to a target core on the host platform.

8. The network interface of claim 1 , further comprising a virtual queue to queue a plurality of reordered data frames to a target core of the host platform.

9. The network interface of claim 1 , wherein the host platform interface comprises a configuration interface for a core of the host platform to configure the packet preprocessor.

10. The network interface of claim 1 , wherein the packet pre-processor is further to alter the endianness of the data sequence.

11. The network interface of claim 1 , wherein the parallel processing operation is selected from the group consisting of single-instruction-multiple-data (SIMD), multiple-instruction-multiple-data (MIMD), and vector processing.

12. The network interface of claim 1 , wherein the packet preprocessor comprises a coprocessor.

13. A modem comprising the network interface of claim 1 .

14. The modem of claim 13 , wherein the modem is a DOCSIS modem.

15. A service provider data center comprising an edge router, wherein the edge router is the DOCSIS modem of claim 14 .

16. One or more tangible, non-transitory computer-readable storage mediums having stored thereon executable instructions for providing a packet preprocessor, the instructions to:
provision an ingress interface;
provision a host platform interface;
receive via the ingress interface a data sequence comprising a plurality of discrete data units;
identify the data sequence as data for a parallel processing operation;
reorder the discrete data units into a reordered data frame, the reordered data frame configured to order the discrete data units for consumption by the parallel operation; and
send the reordered data to a host platform via the host platform interface.

17. The one or more tangible, non-transitory computer-readable mediums of claim 16 , wherein the data sequence is a single data packet.

18. The one or more tangible, non-transitory computer-readable mediums of claim 17 , wherein reordering the discrete data units comprises segmenting the reordered data frame into a plurality of buffers.

19. The one or more tangible, non-transitory computer-readable mediums of claim 16 , wherein the data sequence comprises a plurality of packets, and wherein reordering comprises coalescing the plurality of packets and the reordered data frame comprises a single buffer.

20. The one or more tangible, non-transitory computer-readable mediums of claim 16 , wherein the instructions are further to send the data sequence to the host platform.

21. The one or more tangible, non-transitory computer-readable mediums of claim 16 , wherein the instructions are further to provide the reordered data frame with metadata identifying the data frame as ready for consumption by the parallel processing operation.

22. The one or more tangible, non-transitory computer-readable mediums of claim 16 , wherein the instructions are further to provide a vector switch to switch the reordered data frame to a target core on the host platform.

23. The one or more tangible, non-transitory computer-readable mediums of claim 16 , wherein the instructions are further to provide a virtual queue to queue a plurality of reordered data frames to a target core of the host platform.

24. The one or more tangible, non-transitory computer-readable mediums of claim 16 , wherein the host platform interface comprises a configuration interface for a core of the host platform to configure the packet preprocessor.

25. A computer-implemented method of providing packet pre-processing, comprising:
provisioning an ingress interface;
provisioning a host platform interface;
receiving via the ingress interface a data sequence comprising a plurality of discrete data units;
identifying the data sequence as data for a parallel processing operation;
reordering the discrete data units into a reordered data frame, the reordered data frame configured to order the discrete data units for consumption by the parallel operation; and
sending the reordered data to a host platform via the host platform interface.

26. The method of claim 25 , wherein the data sequence is a single data packet.

Assignees

• Intel Corp

Inventors

• Kantecki Tomasz
• Power Niall
• Browne John J
• Macnamara Christopher
• Doyle Stephen

Classifications

• H04L49/3045

  Virtual queuing · CPC title

• H04L47/34

  ensuring sequence integrity, e.g. using sequence numbers · CPC title

• H04L49/9057 Primary

  Arrangements for supporting packet reassembly or resequencing · CPC title

• H04L49/9021

  Plurality of buffers per packet · CPC title