Inverse pseudo fully-differential amplifier having common-mode feedback control circuit

Patent metadata

Field	Value
Publication number	US-11050386-B2
Application number	US-201916965342-A
Country	US
Kind code	B2
Filing date	Jul 3, 2019
Priority date	Jan 8, 2019
Publication date	Jun 29, 2021
Grant date	Jun 29, 2021

Abstract

An inverse pseudo fully-differential amplifier having a common-mode feedback control circuit and a method for maintaining a stable output common-mode level are provided. The inverse pseudo fully-differential amplifier includes the pseudo fully-differential operation circuit and a common-mode feedback control circuit. The pseudo fully-differential operation circuit includes inverter amplifiers (2) and (3). The inverter amplifiers (2) and (3) respectively have a first feedback control terminal and a second feedback control terminal. Input terminals of the common-mode feedback control circuit are respectively connected with output terminals of the inverter amplifier (2) and (3), and are configured to detect common-mode output voltages of the inverter amplifier (2) and (3). An output terminal of the common-mode feedback control circuit is connected with the first feedback control terminal and the second feedback control terminal, and is configured to generate common-mode feedback to the inverter amplifiers (2) and (3) to maintain a stable common mode output level.

First claim

The invention claimed is:

1. An inverse pseudo fully-differential amplifier having a common-mode feedback control circuit, comprising:
a pseudo fully-differential operation circuit comprising a first inverter amplifier and a second inverter amplifier, wherein the first inverter amplifier has a first feedback control terminal, and the second inverter amplifier has a second feedback control terminal;
the common-mode feedback control circuit, wherein input terminals of the common-mode feedback control circuit are respectively connected with an output terminal of the first inverter amplifier and an output terminal of the second inverter amplifier, an output terminal of the common-mode feedback control circuit is connected with the first feedback control terminal and the second feedback control terminal, and the common-mode feedback control circuit is configured to detect common-mode output voltages of the first inverter amplifier and the second inverter amplifier and generate a feedback control signal, the feedback control signal is inputted to the first feedback control terminal and the second feedback control terminal to regulate gains of the first inverter amplifier and the second inverter amplifier to regulate the common-mode output voltages,
wherein the pseudo fully-differential operation circuit further comprises a ninth switch, a tenth switch, an eighth capacitor and a ninth capacitor, an upper plate of the eighth capacitor is connected with a first input signal, a lower plate of the eighth capacitor is connected with an input terminal of the first inverter amplifier, and the ninth switch is connected in parallel with the first inverter amplifier, an upper plate of the ninth capacitor is connected with a second input signal, a lower plate of the ninth capacitor is connected with an input terminal of the second inverter amplifier, and the tenth switch is connected in parallel with the second inverter amplifier,
the first inverter amplifier has a same circuit as that of the second inverter amplifier, and the circuit of the inverter amplifier comprises a first Positive Channel Metal Oxide Semiconductor (PMOS) transistor, a second PMOS transistor, a third N-Metal Oxide Semiconductor (NMOS) transistor, a fourth NMOS transistor, an eleventh switch, a twelfth switch, a thirteenth switch, a fourteenth switch, a first voltage source and a second voltage source; wherein,
a source of the first PMOS transistor is an input terminal of the circuit of the inverter amplifier, and an output terminal of the second voltage source is an output terminal of the circuit of the inverter amplifier, a drain and a gate of the first PMOS transistor are connected through the thirteenth switch, a source and a gate of the fourth NMOS transistor are connected through the fourteenth switch, a gate of the second PMOS transistor and a gate of the third NMOS transistor are respectively connected with a first reference voltage and a second reference voltage;
during an input signal sampling phase, the eleventh switch, the twelfth switch, the thirteenth switch and the fourteenth switch are all in a turn-on state, a current of the first PMOS transistor flows through the first voltage source, a current of the fourth NMOS transistor flows through the second voltage source, and the second PMOS transistor and the third NMOS transistor are both in an off state; and
during an input signal amplifying phase, the eleventh switch, the twelfth switch, the thirteenth switch and the fourteenth switch are all in a turn-off state, the first PMOS transistor, the second PMOS transistor, the third NMOS transistor and the fourth NMOS transistor constitute a class AB amplifier which is configured to amplify an output current.

2. The inverse pseudo fully-differential amplifier having the common-mode feedback control circuit of claim 1 , wherein the pseudo fully-differential operation circuit further comprises a seventh switch, an eighth switch, a sixth capacitor and a seventh capacitor, one end of the seventh switch is connected with an upper plate of the sixth capacitor, a lower plate of the sixth capacitor is connected with the output terminal of the first inverter amplifier, and other end of the seventh switch is connected with the upper plate of the eighth capacitor; one end of the eighth switch is connected with an upper plate of the seventh capacitor, a lower plate of the seventh capacitor is connected with the output terminal of the second inverter amplifier, and other end of the eighth switch is connected with the upper plate of the ninth capacitor.

3. The inverse pseudo fully-differential amplifier having the common-mode feedback control circuit of claim 2 , further comprising:
an input signal sampling circuit configured to provide the first input signal and the second input signal for the pseudo fully-differential operation circuit.

4. The inverse pseudo fully-differential amplifier having the common-mode feedback control circuit of claim 3 , wherein the input signal sampling circuit comprises a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a fourth capacitor and a fifth capacitor,
the first switch and the third switch are all connected with an upper plate of the fourth capacitor, the second switch and the fourth switch are all connected with an upper plate of the fifth capacitor, other ends of the first switch and the second switch are respectively connected with a first sampling circuit input signal and a second sampling circuit input signal, a lower plate of the fourth capacitor is connected with the fifth switch, a lower plate of the fifth capacitor is connected with the sixth switch, other ends of the fifth switch, the sixth switch, the third switch and the fourth switch are connected with a same level, wherein the lower plate of the fourth capacitor outputs the first input signal, and the lower plate of the fifth capacitor outputs the second input signal.

5. The inverse pseudo fully-differential amplifier having common-mode feedback control circuit of claim 1 , wherein each of the first feedback control terminals of the first inverter amplifier and the second feedback control terminal of the second inverter amplifier is led out from the gate of the fourth NMOS transistor.

6. The inverse pseudo fully-differential amplifier having the common-mode feedback control circuit of claim 1 , wherein the common-mode feedback control circuit comprises a fifteenth switch, a sixteenth switch, a seventeenth switch, an eighteenth switch, a tenth capacitor and an eleventh capacitor,
wherein one end of the fifteenth switch is connected with the output terminal of the first inverter amplifier, one end of the sixteenth switch is connected with the output terminal of the second inverter amplifier, other end of the fifteenth switch is connected with an upper plate of the tenth capacitor, other end of the sixteenth switch is connected with an upper plate of the eleventh capacitor, a lower plate of the tenth capacitor and a lower plate of the eleventh capacitor are connected together and then respectively connected with the first feedback control terminal of the first inverter amplifier and the second feedback control terminal of the second inverter amplifier, to constitute a detection circuit for the common-mode output voltages of the first inverter amplifier and the second inverter amplifier; and
one end of the seventeenth switch is connected with the upper plate of the tenth capacitor, one end of the eighteenth switch is connected with the upper plate of the eleventh capacitor, other end of the seventeenth switch is connected with a common-mode reference voltage, and other end of the eighteenth switch is connected with the common-mode reference voltage, to constitute a comparison circuit for the common-mode output voltag

Assignees

• Beijing Smartchip Microelectronics Tech Co Ltd
• State Grid Information & Telecommunication Group Co Ltd
• State Grid Corp China
• Beijing Smartchip Microelectronics Tech Comp

Inventors

• Wang Yubo
• Tang Xiaoke
• Hu Yi
• Li Dejian
• Shao Jin
• Feng Xi
• Feng Wennan
• Hou Jiali

Classifications

• H03F3/45475

  using IC blocks as the active amplifying circuit · CPC title

• H03F2200/129

  there being a feedback over the complete amplifier · CPC title

• H03F3/45179 Primary

  using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title

• H03F2203/45332

  the AAC comprising one or more capacitors as feedback circuit elements · CPC title

• H03F3/45659 Primary

  Controlling the loading circuit of the differential amplifier · CPC title