Display panel and electronic device including the same

Patent metadata

Field	Value
Publication number	US-11050041-B2
Application number	US-201916516437-A
Country	US
Kind code	B2
Filing date	Jul 19, 2019
Priority date	Nov 2, 2018
Publication date	Jun 29, 2021
Grant date	Jun 29, 2021

Abstract

A display panel includes a peripheral region adjacent to a display region. The display region includes a hole peripheral region, and a recessed region is overlapped with the hole peripheral region. The display panel also includes a barrier layer with a penetrating opening overlapped with the recessed region, a circuit layer on the barrier layer and including transistor and insulating layers, and a device layer including an organic light emitting area coupled to the circuit layer. In addition, a module hole is overlapped with the hole peripheral region and penetrates the base substrate, and a first groove is overlapped with the hole peripheral region and corresponds to a portion of the base substrate that is recessed from a top surface of the barrier layer and that encloses the module hole. The insulating layers include inorganic layers and an organic layer having side portions enclosing the module hole.

First claim

What is claimed is:

1. A display panel including a hole, a display region and a hole peripheral region between the hole and the display region, comprising:
a base substrate including a first groove and a second groove both in the hole peripheral region, the second groove is between the hole and the first groove;
a barrier layer on the base substrate;
a transistor on the barrier layer;
a first electrode coupled to the transistor;
a light emitting layer on the first electrode;
a second electrode on the light emitting layer;
a first inorganic encapsulation layer on the second electrode;
an organic encapsulation layer on the first inorganic encapsulation layer; and
a second inorganic encapsulation layer on the organic encapsulation layer,
wherein the first inorganic encapsulation layer and the second inorganic encapsulation layer are in the second groove,
wherein the first inorganic encapsulation layer is in the first groove,
wherein the second inorganic encapsulation layer is not in the first groove.

2. The display panel of claim 1 , wherein the display panel further includes:
a circuit layer on the barrier layer, the circuit layer including the transistor and a plurality of insulating layers, the plurality of insulating layers includes a first inorganic layer, a second inorganic layer on the first inorganic layer, and an organic layer,
wherein a side portion of each of the first inorganic layer and the second inorganic layer adjacent to the hole encloses the hole and is covered by the organic layer.

3. The display panel of claim 1 , wherein the first groove is filled with organic encapsulation layer.

4. The display panel of claim 1 , further comprising:
a dam between the first groove and the second groove, and the dam includes a first dam portion and a second dam portion sequentially stacked.

5. The display panel of claim 4 , wherein the second dam portion covers a side surface of the first dam portion.

6. The display panel of claim 4 , further comprising:
an interlayer insulation layer between the transistor and the first electrode, the interlayer insulation layer covers the transistor; and
a pixel definition layer between the first electrode and the first inorganic encapsulation layer, the pixel definition layer includes an opening exposing the first electrode.

7. The display panel of claim 6 , wherein the first dam portion has a same material as the interlayer insulation layer, and
the second dam portion has a same material as the pixel definition layer.

8. The display panel of claim 1 , wherein:
a portion of the barrier layer, which covers a portion of the base substrate overlapped with the first groove and the second groove, corresponds to a tip portion, and
the tip portion is covered with the first inorganic encapsulation layer.

9. The display panel of claim 1 , wherein: the first groove and the second groove have a closed loop shape enclosing the hole.

10. The display panel of claim 1 , further comprising:
a planarization layer on the second inorganic encapsulation layer to provide a flat surface.

11. The display panel of claim 10 , wherein the second groove is filled with the planarization layer.

12. The display panel of claim 11 , further comprising:
an input sensing area on the second inorganic encapsulation layer, the input sensing area includes an organic sensing layer covering a sensing electrode.

13. The display panel of claim 12 , wherein the organic sensing layer includes a same material as the planarization layer.

14. The display panel of claim 13 , wherein the hole penetrates the planarization layer.

Assignees

• Samsung Display Co Ltd

Inventors

• Choi Wonwoo
• Kim Sooyoun
• Seo Junghan
• Sung Wooyong
• Lee Seoyeon
• Lee Hyoungsub
• Chang Moonwon
• Chae Seunggun

Classifications

• H10K59/805

  Electrodes · CPC title

• H10K59/8731 Primary

  multilayered coatings having a repetitive structure, e.g. having multiple organic-inorganic bilayers · CPC title

• H10K50/844

  Encapsulations · CPC title

• H10K59/122 Primary

  Pixel-defining structures or layers, e.g. banks · CPC title

• H10K59/40

  OLEDs integrated with touch screens · CPC title