Silicon carbide semiconductor device and power converter

Patent metadata

Field	Value
Publication number	US-11049963-B2
Application number	US-201816757767-A
Country	US
Kind code	B2
Filing date	Dec 18, 2018
Priority date	Dec 19, 2017
Publication date	Jun 29, 2021
Grant date	Jun 29, 2021

Abstract

In SiC-MOSFETs including Schottky diodes, passage of a bipolar current to a well region in an edge portion of an active region cannot be sufficiently reduced, which may reduce the reliability of elements. In a SiC-MOSFET including Schottky diodes, the Schottky diodes formed in a terminal region are made higher in density in a plane direction than those formed in the active region or intervals between the Schottky diodes in the plane direction are shortened, without an ohmic connection between the well and the source in the terminal region.

First claim

The invention claimed is:

1. A silicon carbide semiconductor device, comprising:
a semiconductor substrate made of silicon carbide of a first conductivity type;
a drift layer of the first conductivity type, the drift layer being formed on the semiconductor substrate;
a plurality of first well regions of a second conductivity type, the first well regions being formed in a surface layer of the drift layer;
a plurality of first separation regions of the first conductivity type, the first separation regions being formed adjacent to the first well regions from a surface of the first well regions to the drift layer;
a first Schottky electrode formed on each of the first separation regions, the first Schottky electrode forming a Schottky junction with the first separation region;
an ohmic electrode formed on each of the first well regions;
a second well region of the second conductivity type, the second well region being formed in the surface layer of the drift layer separately from the first well regions;
a plurality of fourth separation regions of the first conductivity type, the fourth separation regions being formed adjacent to the second well region from a surface of the second well region to the drift;
a second Schottky electrode formed on each of the fourth separation regions, the second Schottky electrode forming a Schottky junction with the fourth separation region;
a source region of the first conductivity type, the source region being formed in a surface layer area of each of the first well regions;
a gate insulating film formed on the first well regions and the second well region;
a gate electrode formed on the gate insulating film on the first well regions and the second well region;
a gate pad connected to the gate electrode and formed above the second well region;
a source electrode electrically connected to the first Schottky electrodes, the second Schottky electrodes, and the ohmic electrodes, the source electrode having a non-ohmic connection to the second well region; and
ground auxiliary regions of the second conductivity type, the ground auxiliary regions being adjacent to the second well region through a fifth separation region of the first conductivity type and having an ohmic connection to the source electrode.

2. The silicon carbide semiconductor device according to claim 1 ,
wherein the fourth separation regions are formed at intervals shorter than intervals of the first separation regions.

3. The silicon carbide semiconductor device according to claim 1 ,
wherein the first well regions are separated from the second well region.

4. The silicon carbide semiconductor device according to claim 1 , comprising:
a field insulating film formed on the second well region, the field insulating film being thicker than the gate insulating film; and
a second contact hole formed through the field insulating film, the second contact hole being connected to the second Schottky electrode and the source electrode.

5. The silicon carbide semiconductor device according to claim 4 ,
wherein a boundary between the gate insulating film and the field insulating film is between the first separation region and the fourth separation regions.

6. The silicon carbide semiconductor device according to claim 1 , comprising
a silicon carbide conductive layer formed in an upper layer area of the second well region, the silicon carbide conductive layer being lower in resistance than the second well region.

7. The silicon carbide semiconductor device according to claim 1 ,
wherein the gate electrode is formed above a portion between the fourth separation regions.

8. The silicon carbide semiconductor device according to claim 1 ,
wherein the gate electrode formed above a portion between the fourth separation regions is wider than the gate electrode formed above a portion between the first separation regions near the first well regions.

9. The silicon carbide semiconductor device according to claim 1 ,
wherein the second Schottky electrode is formed partly on the second well region, and
a region of the second well region that is in contact with the second Schottky electrode is lower in impurity concentration than a region of the second well region that is distant from the second Schottky electrode in a depth direction.

10. The silicon carbide semiconductor device according to claim 4 ,
wherein the second Schottky electrode is formed on the fourth separation regions formed in the second contact hole in a planar view and on auxiliary regions of the second conductivity type that are formed between the fourth separation regions, and
a region of the auxiliary regions that is in contact with the second Schottky electrode is lower in impurity concentration than a region of the auxiliary regions that is distant from the second Schottky electrode in a depth direction.

11. The silicon carbide semiconductor device according to claim 1 ,
wherein the fourth separation regions are formed inside or between the ground auxiliary regions in a planar view.

12. The silicon carbide semiconductor device according to claim 1 ,
wherein the second Schottky electrode is formed across the second well region, the fifth separation region, and the ground auxiliary regions.

13. The silicon carbide semiconductor device according to claim 1 , comprising
a second ohmic electrode between the ground auxiliary regions and the source electrode.

14. The silicon carbide semiconductor device according to claim 1 , comprising
a second contact region formed in an upper portion of the ground auxiliary regions, the second contact region being higher in impurity concentration of the second conductivity type than the ground auxiliary regions.

15. A power converter, comprising:
a main conversion circuit including the silicon carbide semiconductor device according to claim 1 , and converting an input power to output a resulting power;
a drive circuit outputting, to the silicon carbide semiconductor device, a drive signal for driving the silicon carbide semiconductor device; and
a control circuit outputting, to the drive circuit, a control signal for controlling the drive circuit.

16. The silicon carbide semiconductor device according to claim 1 ,
wherein the fourth separation regions are formed in a plane direction at a density higher than a density of the first separation regions.

Assignees

• Mitsubishi Electric Corp

Inventors

• Hino Shiro
• NAGAHISA Yuichi
• Sadamatsu Koji
• Hatta Hideyuki
• Kawahara Kotaro

Classifications

• H10D64/64

  Electrodes comprising a Schottky barrier to a semiconductor · CPC title

• H10D62/8325

  Silicon carbide · CPC title

• H10D62/127

  of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs · CPC title

• H10D8/60

  Schottky-barrier diodes · CPC title

• H10D30/60

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title