Semiconductor structure with capacitor landing pad and method of making the same

Patent metadata

Field	Value
Publication number	US-11049863-B2
Application number	US-201815889182-A
Country	US
Kind code	B2
Filing date	Feb 5, 2018
Priority date	Feb 24, 2017
Publication date	Jun 29, 2021
Grant date	Jun 29, 2021

Abstract

A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.

First claim

What is claimed is:

1. A semiconductor structure with capacitor landing pads, comprising:
a substrate;
a capacitor contact plug disposed on the substrate;
a capacitor landing pad contacting and electrically connecting the capacitor contact plug;
a bit line disposed on the substrate;
a bit line mask contacting the bit line; and

a dielectric layer surrounding the capacitor landing pad, wherein the dielectric layer comprises a bottommost surface lower than a top surface of the bit line, and a topmost surface of the capacitor landing pad and a topmost surface of the dielectric layer are aligned, and a topmost surface of the bit line mask is lower than the topmost surface of the capacitor landing pad.

2. The semiconductor structure with capacitor landing pads of claim 1 , wherein a first distance is disposed between the topmost surface of the capacitor landing pad and a top surface of the substrate, a second distance is disposed between the top surface of the bit line and the top surface of the substrate, and the first distance is greater than the second distance.

3. The semiconductor structure with capacitor landing pads of claim 1 , wherein the dielectric layer forms a chessboard pattern.

4. The semiconductor structure with capacitor landing pads of claim 1 , wherein the bit line mask is between the capacitor landing pad and the bit line.

5. The semiconductor structure with capacitor landing pads of claim 1 , wherein the dielectric layer is in a shape of a meat cleaver including a handle and a blade, a topmost surface of the blade is aligned with the topmost surface of the capacitor landing pad, a bottommost surface of the handle is lower than the top surface of the bit line, and the blade is wider than the handle.

Assignees

• United Microelectronics Corp
• Fujian Jinhua Integrated Circuit Co Ltd

Inventors

• Feng li-wei
• Tzou Shih-Fang
• Ho Chien-Ting
• Wang Ying-Chiao
• Chen Yu-Ching
• Chuang Hui-Ling
• Yu Kuei-Hsuan

Classifications

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H01L27/10814

  Electricity · mapped topic

• H01L27/10823

  Electricity · mapped topic

• H01L27/10855 Primary

  Electricity · mapped topic

• H10B12/0335 Primary

  Making a connection between the transistor and the capacitor, e.g. plug · CPC title