Circuit substrate

Patent metadata

Field	Value
Publication number	US-11049831-B2
Application number	US-201916550402-A
Country	US
Kind code	B2
Filing date	Aug 26, 2019
Priority date	Mar 3, 2017
Publication date	Jun 29, 2021
Grant date	Jun 29, 2021

Abstract

A circuit substrate that includes a substrate having a major surface, a multilayer body on the major surface, and an insulating layer that covers the major surface. The multilayer body includes a first layer and a second layer that overlies the first layer. The first layer is made of a first metal as a main material thereof, and the second layer is made of a second metal as a main material thereof. The second metal has a higher solder wettability than the first metal. As viewed perpendicular to the major surface, the insulating layer is spaced from and surrounds the surface of the second layer so as to define a recess between the multilayer body and the insulating layer.

First claim

The invention claimed is:

1. A circuit substrate comprising:
a substrate having a major surface;
a multilayer body on the major surface, the multilayer body including:
a first layer made of a first metal as a main material thereof,
a second layer made of a second metal as a main material thereof, the second layer overlying the first layer, and the second metal having a higher solder wettability than the first metal, wherein the first layer and the second layer have a rectangular shape as viewed perpendicular to the major surface of the substrate, and
a third layer made of the first metal as a main material thereof, the third layer positioned between the first layer and the major surface of the substrate and extending beyond side surfaces of the first layer; and

an insulating layer on the major surface, the insulating layer surrounding and spaced from a surface of the second layer as viewed perpendicular to the major surface such that a recess is defined between the multilayer body and the insulating layer and an entirety of a bottom portion of the recess between the multilayer body and the insulating layer is the third layer.

2. The circuit substrate according to claim 1 , wherein the insulating layer surrounds and is spaced from the side surfaces of the first layer as viewed perpendicular to the major surface such that the recess is also defined between the first layer and the insulating layer.

3. The circuit substrate according to claim 1 , wherein the first metal is Cu and the second metal is Au.

4. The circuit substrate according to claim 1 , wherein each of the side surfaces of the first layer are located at a same position as a corresponding side surface of the second layer.

5. The circuit substrate according to claim 1 , wherein the third layer is electrically connected to the first layer.

6. The circuit substrate according to claim 5 , wherein the third layer is integral with the first layer.

7. The circuit substrate according to claim 1 , further comprising an intermediate layer between the first layer and the second layer, the intermediate layer having electrical conductivity.

8. The circuit substrate according to claim 7 , wherein the third layer is electrically connected to the first layer.

9. The circuit substrate according to claim 8 , wherein the third layer is integral with the first layer.

10. The circuit substrate according to claim 7 , further comprising an antioxidant film covering at least a surface of the first layer of the multilayer body.

11. The circuit substrate according to claim 10 , wherein the antioxidant film further covers at least a surface of the third layer.

12. The circuit substrate according to claim 1 , further comprising an antioxidant film covering at least a surface of the first layer of the multilayer body.

13. The circuit substrate according to claim 12 , wherein the antioxidant film further covers at least a surface of the third layer.

Assignees

• Murata Manufacturing Co

Inventors

• Hatase Minoru
• Mizushiro Masaaki

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/287

  Flow barriers · CPC title

• H10W70/69 Primary

  Insulating materials thereof · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W72/07236

  Soldering or alloying · CPC title