Self-aligned interconnection for integrated circuits

Patent metadata

Field	Value
Publication number	US-11049769-B2
Application number	US-201816111004-A
Country	US
Kind code	B2
Filing date	Aug 23, 2018
Priority date	Aug 23, 2012
Publication date	Jun 29, 2021
Grant date	Jun 29, 2021

Abstract

Methods and structures provide horizontal conductive lines of fine pitch and self-aligned contacts extending from them, where the contacts have at least one dimension with a more relaxed pitch. Buried hard mask materials permit self-alignment of the lines and contacts without a critical mask, such as for word-line electrode lines and word-line contacts in a memory device.

First claim

What is claimed is:

1. An integrated circuit comprising:
a first insulating layer;
a second insulating layer;
a hard mask formed between the first insulating layer and the second insulating layer, the hard mask comprising a slot, wherein a portion of the second insulating layer contacts a surface of the first insulating layer at the slot;
a plurality of conductive interconnects contacting a surface of the hard mask;
a conductive line contacting the second insulating layer and intersecting the slot; and
a conductive contact comprising the plurality of conductive interconnects and extending from the conductive line through the hard mask and the first insulating layer.

2. The integrated circuit of claim 1 , further comprising:
an interlevel dielectric layer interleaved between the plurality of conductive interconnects, the second insulating layer comprising the interlevel dielectric layer.

3. The integrated circuit of claim 2 , wherein a portion of the interlevel dielectric layer contacts the surface of the first insulating layer.

4. The integrated circuit of claim 2 , wherein a sidewall of the hard mask contacts a sidewall of the interlevel dielectric layer.

5. The integrated circuit of claim 2 , wherein a conductive interconnect of the plurality of conductive interconnects is in contact with a pair of sidewalls associated with the first insulating layer.

6. The integrated circuit of claim 2 , wherein a conductive interconnect of the plurality of conductive interconnects is in contact with a pair of sidewalls associated with the second insulating layer.

7. The integrated circuit of claim 1 , wherein each conductive interconnect of the plurality of conductive interconnects comprises a first width in a first direction and a second width in a second direction different than the first direction based at least in part on a feature dimension associated with the hard mask.

8. The integrated circuit of claim 1 , wherein a width of the slot is based at least in part on a feature dimension associated with the hard mask.

9. The integrated circuit of claim 1 , further comprising:
an etch stop layer formed between the first insulating layer and a substrate, wherein the conductive line intersects the etch stop layer.

10. An integrated circuit comprising:
a first insulating layer;
a second insulating layer;
a hard mask formed between the first insulating layer and the second insulating layer, the hard mask comprising a slot, wherein a portion of the second insulating layer contacts a surface of the first insulating layer at the slot;
a conductive line contacting the second insulating layer and intersecting the slot;
a conductive contact extending from the conductive line through the hard mask and the first insulating layer; and
a plurality of trenches extending through the hard mask, the first insulating layer, and the second insulating layer, wherein the plurality of trenches are interleaved between the second insulating layer.

11. A memory device, comprising:
a hard mask formed between a first insulating layer and a second insulating layer, the hard mask comprising a slot, wherein a portion of the second insulating layer contacts a surface of the first insulating layer at the slot;
a plurality of trenches, the plurality of trenches extending through the hard mask, the first insulating layer, and the second insulating layer, wherein the plurality of trenches are interleaved between the second insulating layer; and
a conductive contact electrically coupled to a conductive line having a width greater than or equal to a width of at least one trench of the plurality of trenches, the conductive contact extending from the conductive line through the hard mask and the first insulating layer.

12. The memory device of claim 11 , further comprising:
a plurality of conductive interconnects contacting a surface of the hard mask, wherein the conductive contact further comprises the plurality of conductive interconnects.

13. The memory device of claim 12 , further comprising:
an interlevel dielectric layer interleaved between the plurality of conductive interconnects, the second insulating layer comprising the interlevel dielectric layer.

14. The memory device of claim 13 , wherein a portion of the interlevel dielectric layer contacts the surface of the first insulating layer.

15. The memory device of claim 13 , wherein a sidewall of the hard mask contacts a sidewall of the interlevel dielectric layer.

16. The memory device of claim 13 , wherein a conductive interconnect of the plurality of conductive interconnects is in contact with a pair of sidewalls associated with the first insulating layer.

17. The memory device of claim 13 , wherein a conductive interconnect of the plurality of conductive interconnects is in contact with a pair of sidewalls associated with the second insulating layer.

18. The memory device of claim 12 , wherein each conductive interconnect of the plurality of conductive interconnects comprises a first width in a first direction and a second width in a second direction different than the first direction based at least in part on a feature dimension associated with the hard mask.

19. The memory device of claim 11 , further comprising:
an etch stop layer formed between the first insulating layer and a substrate, wherein the conductive line intersects the etch stop layer.

Assignees

• Micron Technology Inc

Inventors

• Pellizzer Fabio
• Rigano Antonino
• Somaschini Roberto

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/086

  involving buried masks · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title