Display control circuit

US11049471B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11049471-B2
Application numberUS-201916524264-A
CountryUS
Kind codeB2
Filing dateJul 29, 2019
Priority dateJul 29, 2019
Publication dateJun 29, 2021
Grant dateJun 29, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

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A display control circuit transforms a plurality of input points of an input image to a plurality of target subpixels of a display panel. In the display panel, a first row of the target subpixels and a second row of the target subpixels are non-aligned in a vertical direction. The display control circuit includes a subpixel rendering circuit. The subpixel rendering circuit maps a first row of the input points to the first row of the target subpixels, and maps a second row of the input points to the second row of the target subpixels. The coordinates of the first row of the input points are respectively equivalent to the coordinates of the first row of the target subpixels. The coordinates of the second row of the input points are respectively equivalent to the coordinates of the second row of the target subpixels being shifted in a horizontal direction.

First claim

Opening claim text (preview).

What is claimed is: 1. A display control circuit, applied to transform a plurality of input points of an input image to a plurality of target subpixels of a display panel, wherein the input points have at least a first colored input point, a second colored input points, and a third colored input point, and the target subpixels have at least a first colored subpixel, a second colored subpixel, and a third colored subpixel, wherein a first row of the target subpixels and a second row of the target subpixels are non-aligned in a vertical direction, wherein the display control circuit comprises: a subpixel rendering circuit, configured to map a first row of the input points to the first row of the target subpixels, wherein a plurality of coordinates of the first row of the target subpixels are respectively equivalent to a plurality of coordinates of the first row of the input points, and map a second row of the input points to the second row of the target subpixels, wherein a plurality of coordinates of the first colored subpixels of the second row of the target subpixels are respectively equivalent to a plurality of coordinates of the first colored input points of the second row of the input points being shifted in a horizontal direction, and a plurality of coordinates of the second row of the second and the third colored subpixels of the target subpixels are respectively equivalent to a plurality of coordinates of the second and the third colored input points of the second row of the input points. 2. The display control circuit according to claim 1 , wherein the subpixel rendering circuit is further configured to map a third row of the input points to a third row of the target subpixels, wherein a plurality of coordinates of the third row of the target subpixels are respectively equivalent to a plurality of coordinates of the third row of the input points. 3. The display control circuit according to claim 2 , wherein the first row of the target subpixels and the third row of the target subpixels are aligned in the vertical direction. 4. A display control circuit, applied to transform a plurality of input points of an input image to a plurality of target subpixels of a display panel, wherein the input points have at least a first colored input point, a second colored input point, and a third colored input point, and the target subpixels have at least a first colored subpixel, a second colored subpixel, and a third colored subpixel, wherein the display control circuit: a subpixel rendering circuit, configured to map a first input point among the input points to a first target subpixel among the target subpixels, wherein a coordinate of the first target subpixel is equivalent to a coordinate of the first input point, and map a second input point among the input points to a second target subpixel among the target subpixels, wherein a coordinate of the first colored subpixel of the second target subpixel is equivalent to a coordinate of the first colored input point of the second input point with a coordinate shift, and coordinates of the second and the third colored subpixels of the second target subpixel are respectively equivalent to coordinates of the second and the third colored input points of the second input point. 5. The display control circuit according to claim 4 , wherein the first input point and the second input point are respectively located at a first row and a second row of the input image. 6. The display control circuit according to claim 4 , wherein the first target subpixel and the second target subpixel are respectively located at a first row and a second row of the display panel. 7. The display control circuit according to claim 4 , wherein the coordinate shift is in a first direction. 8. The display control circuit according to claim 7 , wherein the first target subpixel and the second target subpixel are arranged along a second direction, and the first direction and the second direction are perpendicular. 9. The display control circuit according to claim 7 , wherein the first target subpixel and the second target subpixel are arranged along the first direction.

Assignees

Inventors

Classifications

  • for control of colour parameters, e.g. colour temperature · CPC title

  • G09G5/02Primary

    characterised by the way in which colour is displayed {(details of colour display specific for CRTs G09G1/28; specific for flat matrix panels other than liquid crystal displays G09G3/2003; specific for liquid crystal displays G09G3/3607)} · CPC title

  • with two or more screen areas displaying information with different brightness or colours · CPC title

  • Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components · CPC title

  • Improvement of perceived resolution by subpixel rendering · CPC title

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What does patent US11049471B2 cover?
A display control circuit transforms a plurality of input points of an input image to a plurality of target subpixels of a display panel. In the display panel, a first row of the target subpixels and a second row of the target subpixels are non-aligned in a vertical direction. The display control circuit includes a subpixel rendering circuit. The subpixel rendering circuit maps a first row of t…
Who is the assignee on this patent?
Novatek Microelectronics Corp
What technology area does this patent fall under?
Primary CPC classification G09G5/02. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jun 29 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).